AD5533
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Limit at TMIN, TMAX
Parameter1, 2
(A Version)
Unit
Conditions/Comments
t1
t2
t3
t4
t5
t6
0
0
50
50
20
0
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR Setup Time
CS to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
A4–A0, CAL, OFFS_SEL to WR Setup Time
A4–A0, CAL, OFFS_SEL to WR Hold Time
NOTES
1See Interface Timing Diagram.
2Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACE
Limit at TMIN, TMAX
Parameter1, 2
(A Version)
Unit
Conditions/Comments
fCLKIN
t1
t2
t3
t4
t5
t6
t73
t83
t9
20
20
20
10
50
10
5
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
DIN Setup Time
DIN Hold Time
SYNC Falling Edge to SCLK Rising Edge Setup Time
SCLK Rising Edge to DOUT Valid
SCLK Falling Edge to DOUT High Impedance
10th SCLK Falling Edge to SYNC Falling Edge for Readback
5
20
60
400
t10
NOTES
1See Serial Interface Timing Diagrams.
2Guaranteed by design and characterization, not production tested.
3These numbers are measured with the load circuit of Figure 2.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAM
CS
I
OL
200A
TO
OUTPUT
PIN
1.6V
WR
C
50pF
L
I
200A
OH
A4–A0, CAL,
OFFS SEL
Figure 1. Parallel Write (SHA Mode Only)
Figure 2. Load Circuit for DOUT Timing Specifications
REV. 0
–4–