32-Channel, 3 V/5 V, Single-Supply,
14-Bit denseDAC
Data Sheet
AD5382
FEATURES
INTEGRATED FUNCTIONS
Guaranteed monotonic
Channel monitor
INL error: 4 LSB max
Simultaneous output update via
LDAC
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User interfaces:
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
Parallel
APPLICATIONS
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,
featuring data readback)
Variable optical attenuators (VOAs)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
I2C-compatible
Robust 6.5 kV HBM and 2 kV FICDM ESD rating
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
DVDD (×3)
DGND (×3)
AVDD (×4)
AGND (×4)
DAC_GND (×4)
REFGND
REFOUT/REFIN SIGNAL_GND (×4)
PD
SER/PAR
AD5382
1.25V/2.5V
REFERENCE
FIFO EN
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO
14
14
14
14
14
14
14
14
14
14
14
14
14
INPUT
REG0
DAC
REG0
DAC 0
VOUT0
DB13/(DIN/SDA)
14
14
m REG0
c REG0
DB12/(SCLK/SCL)
FIFO
+
STATE
MACHINE
+
2
DB11/(SPI/I C)
R
R
R
R
R
R
R
R
DB10
INTERFACE
CONTROL
LOGIC
14
INPUT
REG1
DAC
REG1
DAC 1
DB0
CONTROL
LOGIC
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
14
14
A4
A0
m REG1
c REG1
REG0
REG1
RESET
BUSY
CLR
14
INPUT
REG6
DAC
REG6
DAC 6
POWER-ON
RESET
14
14
m REG6
c REG6
14
INPUT
REG7
DAC
REG7
VOUT0………VOUT31
DAC 7
VOUT7
VOUT8
14
14
MON_IN1
MON_IN2
MON_IN3
MON_IN4
m REG7
c REG7
36-TO-1
MUX
VOUT31
×4
MON_OUT
LDAC
Figure 1.
Rev. C
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