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AD5382BST-REEL PDF预览

AD5382BST-REEL

更新时间: 2024-11-23 19:45:51
品牌 Logo 应用领域
亚德诺 - ADI 输入元件转换器
页数 文件大小 规格书
40页 753K
描述
IC PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP100, 14 X 14 MM, LQFP-100, Digital to Analog Converter

AD5382BST-REEL 数据手册

 浏览型号AD5382BST-REEL的Datasheet PDF文件第2页浏览型号AD5382BST-REEL的Datasheet PDF文件第3页浏览型号AD5382BST-REEL的Datasheet PDF文件第4页浏览型号AD5382BST-REEL的Datasheet PDF文件第5页浏览型号AD5382BST-REEL的Datasheet PDF文件第6页浏览型号AD5382BST-REEL的Datasheet PDF文件第7页 
32-Channel, 3 V/5 V, Single-Supply,  
14-Bit denseDAC  
Data Sheet  
AD5382  
FEATURES  
INTEGRATED FUNCTIONS  
Guaranteed monotonic  
Channel monitor  
INL error: 4 LSB max  
Simultaneous output update via  
LDAC  
On-chip 1.25 V/2.5 V, 10 ppm/°C reference  
Temperature range: –40°C to +85°C  
Rail-to-rail output amplifier  
Power-down mode  
Package type: 100-lead LQFP (14 mm × 14 mm)  
User interfaces:  
Clear function to user-programmable code  
Amplifier boost mode to optimize slew rate  
User-programmable offset and gain adjust  
Toggle mode enables square wave generation  
Thermal monitor  
Parallel  
APPLICATIONS  
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,  
featuring data readback)  
Variable optical attenuators (VOAs)  
Level setting (ATE)  
Optical micro-electro-mechanical systems (MEMS)  
Control systems  
I2C-compatible  
Robust 6.5 kV HBM and 2 kV FICDM ESD rating  
Instrumentation  
FUNCTIONAL BLOCK DIAGRAM  
DVDD (×3)  
DGND (×3)  
AVDD (×4)  
AGND (×4)  
DAC_GND (×4)  
REFGND  
REFOUT/REFIN SIGNAL_GND (×4)  
PD  
SER/PAR  
AD5382  
1.25V/2.5V  
REFERENCE  
FIFO EN  
CS/(SYNC/AD0)  
WR/(DCEN/AD1)  
SDO  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
INPUT  
REG0  
DAC  
REG0  
DAC 0  
VOUT0  
DB13/(DIN/SDA)  
14  
14  
m REG0  
c REG0  
DB12/(SCLK/SCL)  
FIFO  
+
STATE  
MACHINE  
+
2
DB11/(SPI/I C)  
R
R
R
R
R
R
R
R
DB10  
INTERFACE  
CONTROL  
LOGIC  
14  
INPUT  
REG1  
DAC  
REG1  
DAC 1  
DB0  
CONTROL  
LOGIC  
VOUT1  
VOUT2  
VOUT3  
VOUT4  
VOUT5  
VOUT6  
14  
14  
A4  
A0  
m REG1  
c REG1  
REG0  
REG1  
RESET  
BUSY  
CLR  
14  
INPUT  
REG6  
DAC  
REG6  
DAC 6  
POWER-ON  
RESET  
14  
14  
m REG6  
c REG6  
14  
INPUT  
REG7  
DAC  
REG7  
VOUT0………VOUT31  
DAC 7  
VOUT7  
VOUT8  
14  
14  
MON_IN1  
MON_IN2  
MON_IN3  
MON_IN4  
m REG7  
c REG7  
36-TO-1  
MUX  
VOUT31  
×4  
MON_OUT  
LDAC  
Figure 1.  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113© 2004–2012 Analog Devices, Inc. All rights reserved.  

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