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AD5370BCPZ-REEL7 PDF预览

AD5370BCPZ-REEL7

更新时间: 2024-02-09 16:45:23
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
28页 431K
描述
40-Channel, 16-Bit, Serial Input, Voltage-Output DAC

AD5370BCPZ-REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC64,.35SQ,20针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.74
最大模拟输出电压:15.1 V最小模拟输出电压:-15.1 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:S-XQCC-N64
JESD-609代码:e3长度:9 mm
最大线性误差 (EL):0.0061%湿度敏感等级:3
标称负供电电压:-15 V位数:16
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC64,.35SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3/5,+-12/+-16.5 V认证状态:Not Qualified
座面最大高度:1 mm最大稳定时间:30 µs
标称安定时间 (tstl):20 µs子类别:Other Converters
最大压摆率:20 mA标称供电电压:15 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:9 mm
Base Number Matches:1

AD5370BCPZ-REEL7 数据手册

 浏览型号AD5370BCPZ-REEL7的Datasheet PDF文件第1页浏览型号AD5370BCPZ-REEL7的Datasheet PDF文件第2页浏览型号AD5370BCPZ-REEL7的Datasheet PDF文件第4页浏览型号AD5370BCPZ-REEL7的Datasheet PDF文件第5页浏览型号AD5370BCPZ-REEL7的Datasheet PDF文件第6页浏览型号AD5370BCPZ-REEL7的Datasheet PDF文件第7页 
AD5370  
GENERAL DESCRIPTION  
The AD53701 contains forty 16-bit DACs in a single 64-lead  
LFCSP and a 64-lead LQFP. The device provides buffered  
voltage outputs with a span that is 4× the reference voltage. The  
gain and offset of each DAC channel can be independently  
trimmed to remove errors. For even greater flexibility, the device is  
divided into five groups of eight DACs. Three offset DAC channels  
allow the output range of blocks to be adjusted. Group 0 can be  
adjusted by Offset DAC 0, Group 1 can be adjusted by Offset  
DAC 1, and Group 2 to Group 4 can be adjusted by Offset DAC 2.  
The AD5370 has a high speed serial interface that is compatible  
with SPI, QSPI™, MICROWIRE™, and DSP interface standards  
and can handle clock speeds of up to 50 MHz.  
The DAC registers are updated on receipt of new data. All the  
LDAC  
outputs can be updated simultaneously by taking the  
input low. Each channel has a programmable gain and an offset  
adjust register to allow removal of gain and offset errors.  
Each DAC output is gained and buffered on chip with respect to  
an external SIGGNDx input. The DAC outputs can also be  
The AD5370 offers guaranteed operation over a wide supply  
range, with VSS from −16.5 V to −4.5 V and VDD from +9 V to  
+16.5 V. The output amplifier headroom requirement is 1.4 V  
operating with a load current of 1 mA.  
CLR  
switched to SIGGNDx via the  
pin.  
1 Protected by U.S. Patent No. 5,969,657; other patents pending.  
Table 1. High Channel Count Bipolar DACs  
Model  
Resolution  
16 bits  
14 bits  
16 bits  
14 bits  
16 bits  
14 bits  
16 bits  
14 bits  
14 bits  
14 bits  
Nominal Output Span  
4 × VREF (20 V)  
4 × VREF (20 V)  
4 × VREF (20 V)  
4 × VREF (20 V)  
4 × VREF (12 V)  
4 × VREF (12 V)  
4 × VREF (12 V)  
4 × VREF (12 V)  
8.75 V  
Output Channels  
Linearity Error (LSB)  
AD5360  
AD5361  
AD5362  
AD5363  
AD5370  
AD5371  
AD5372  
AD5373  
AD5378  
AD5379  
16  
16  
8
4
1
4
1
4
1
4
1
3
3
8
40  
40  
32  
32  
32  
40  
8.75 V  
Rev. 0 | Page 3 of 28  
 
 

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