8-Channel, 16/14-Bit,
Serial Input, Voltage-Output DAC
Preliminary Technical Data
AD5362/AD5363
SPI compatible serial interface
FEATURES
2.5 V to 5.5 V JEDEC-compliant digital levels
Power-on reset
8-channel DAC in 52-LQFP and 56-LFCSP
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of -10 V to +10 V
Multiple output spans available
Temperature Monitoring Function
Channel Monitoring Multiplexer
GPIO Function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Instrumentation
Industrial Control System
PLC Analog I/O Cards
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Precision Medical Instruments
FUNCTIONAL BLOCK DIAGRAM
DVCC
VDD
VSS
AGND DNGD
LDAC
VREF0
TEMP
SENSOR
AD5362, n = 16
AD5363, n = 14
TEMP_OUT
PEC
GROUP 0
BUFFER
14
n
8
14
n
OFFSET
DAC 0
OFS0
REGISTER
CONTROL
REGISTER
4
4
A/B SELECT
TO
MUX 2's
BUFFER
REGISTER
MON_IN0
MON_IN1
VOUT0 -
VOUT7
OUTPUT BUFFER
AND POWER
DOWN CONTROL
VOUT0
VOUT1
VOUT2
n
n
X2A REGISTER
DAC 0
REGISTER
n
MUX
2
A/B
DAC 0
X1 REGISTER
6
2
MUX
X2B REGISTER
n
MUX
n
n
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
M REGISTER
C REGISTER
·
·
·
·
·
·
·
·
·
·
·
·
n
MON_OUT
GPIO
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
GPIO
REGISTER
BIN/2SCOMP
SYNC
SDI
OUTPUT BUFFER
AND POWER
·
VOUT3
n
n
n
n
n
X2A REGISTER
n
DAC 3
A/B
MUX
2
DAC 3
X1 REGISTER
DOWN CONTROL
REGISTER
SIGGND0
MUX
X2B REGISTER
n
n
M REGISTER
C REGISTER
SERIAL
INTERFACE
n
SCLK
VREF1
GROUP 1
SDO
14
n
14
n
OFFSET
DAC 1
OFS1
REGISTER
BUSY
4
4
TO
MUX 2's
A/B SELECT
REGISTER
BUFFER
RESET
CLR
OUTPUT BUFFER
AND POWER
DOWN CONTROL
VOUT4
VOUT5
VOUT6
n
n
n
X2A REGISTER
DAC 0
REGISTER
n
A/B
MUX
2
DAC 0
X1 REGISTER
MUX
X2B REGISTER
n
n
·
·
·
·
·
·
·
·
·
·
·
M REGISTER
C REGISTER
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
STATE
MACHINE
n
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
n
OUTPUT BUFFER
AND POWER
·
VOUT7
n
n
n
n
n
POWER-ON
RESET
X2A REGISTER
DAC 3
n
A/B
MUX
2
DAC 3
X1 REGISTER
DOWN CONTROL
SIGGND1
REGISTER
MUX
X2B REGISTER
n
n
M REGISTER
C REGISTER
n
AD5362/
AD5363
5362-0001B
Figure 1.
AD5362/AD5363—Protected by U.S. Patent No. 5,969,657; other patents pending
Rev. PrF
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