5秒后页面跳转
捷配首页

Datasheet > 转换器 > 数模转换器> AD5328
AD5328 PDF预览

AD5328

更新时间： 2024-02-03 05:50:38
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
19页 309K
描述
2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

阅读下载

获取价格

AD5328 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：ROHS COMPLIANT, MO-153AB, TSSOP-16针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.26
Is Samacsys：N最大模拟输出电压：5.499 V
最小模拟输出电压：0.001 V转换器类型：D/A CONVERTER
输入位码：BINARY输入格式：SERIAL
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：5 mm最大线性误差 (EL)：0.293%
湿度敏感等级：1位数：12
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
座面最大高度：1.2 mm最大稳定时间：10 µs
标称安定时间 (tstl)：8 µs子类别：Other Converters
最大压摆率：1.8 mA标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmBase Number Matches：1

AD5328 数据手册

 浏览型号AD5328的Datasheet PDF文件第2页浏览型号AD5328的Datasheet PDF文件第3页浏览型号AD5328的Datasheet PDF文件第4页浏览型号AD5328的Datasheet PDF文件第6页浏览型号AD5328的Datasheet PDF文件第7页浏览型号AD5328的Datasheet PDF文件第8页 
AD5308/AD5318/AD5328  
PIN CONFIGURATION  
LDAC  
SYNC  
16 SCLK  
15 DIN  
1
2
3
4
5
6
7
8
AD5308/  
AD5318/  
AD5328  
TOP VIEW  
(Not to Scale)  
V
14 GND  
DD  
V
V
V
V
V
H
G
F
V
A
B
C
D
13  
12  
11  
10  
9
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
V
V
V
E
EFGH  
REF  
V
ABCD  
REF  
PIN FUNCTION DESCRIPTIONS  
Pin No. Mnemonic  
Function  
1
LDAC  
This active low-control input transfers the contents of the input registers to their respective DAC registers.  
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.  
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.  
2
SYNC  
Active Low-Control Input. This is the frame synchronization signal for the input data. When SYNC goes  
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in  
on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the  
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device.  
3
VDD  
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be  
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.  
4
5
6
7
8
V
V
V
V
V
OUTA  
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.  
OUTB  
OUTC  
OUTD  
REFABCD  
Reference Input Pin for DACs A, B, C, and D. It may be configured as a buffered, unbuffered, or VDD  
input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range  
from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.  
9
V
REFEFGH  
Reference Input Pin for DACs E, F, G, and H. It may be configured as a buffered, unbuffered, or VDD  
input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range  
from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.  
10  
11  
12  
13  
14  
15  
V
V
V
V
OUTE  
OUTF  
OUTG  
OUTH  
Buffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.  
Ground Reference Point for All Circuitry on the Part.  
GND  
DIN  
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling  
edge of the serial clock input. The DIN input buffer is powered down after each write cycle.  
16  
SCLK  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock  
input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after  
each write cycle.  
REV. B  
–5–  
12345678...19

下载PDF

与AD5328相关器件

型号 品牌 描述 获取价格 数据表
AD5328ARU ADI 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

获取价格
AD5328ARU-REEL7 ADI 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

获取价格
AD5328ARUZ ADI 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

获取价格
AD5328ARUZ-REEL7 ADI 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

获取价格
AD5328BRU ADI 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

获取价格
AD5328BRU-REEL ADI 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

获取价格

与AD5328相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证