AD532J

更新时间： 2024-01-06 21:03:30

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
7页	139K
描述
Internally Trimmed Integrated Circuit Multiplier

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD532J 技术参数

Source Url Status Check Date：	2013-05-01 14:56:12.241	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Not Recommended
零件包装代码：	SMT	包装说明：	TO-100, CAN10,.23
针数：	10	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	7.53	模拟集成电路 - 其他类型：	ANALOG MULTIPLIER OR DIVIDER
标称带宽：	1 MHz	JESD-30 代码：	O-MBCY-W10
JESD-609代码：	e0	负电源电压最大值（Vsup）：	-22 V
负电源电压最小值（Vsup）：	-10 V	标称负供电电压 (Vsup)：	-15 V
最大负输入电压：	-10 V	功能数量：	1
端子数量：	10	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	METAL
封装代码：	TO-100	封装等效代码：	CAN10,.23
封装形状：	ROUND	封装形式：	CYLINDRICAL
峰值回流温度（摄氏度）：	NOT APPLICABLE	最大正输入电压：	10 V
电源：	+-15 V	认证状态：	Not Qualified
子类别：	Analog Computational Functions	最大供电电流 (Isup)：	6 mA
最大供电电压 (Vsup)：	22 V	最小供电电压 (Vsup)：	10 V
标称供电电压 (Vsup)：	15 V	表面贴装：	NO
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn63Pb37)
端子形式：	WIRE	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT APPLICABLE	Base Number Matches：	1

AD532J 数据手册

Internally Trimmed

Integrated Circuit Multiplier

AD532

FEATURES

PIN CONFIGURATIONS

Pretrimmed to ؎1.0% (AD532K)

No External Components Required

Guaranteed ؎1.0% max 4-Quadrant Error (AD532K)

Diff Inputs for (X₁– X₂) (Y₁– Y₂)/10 V Transfer Function

Monolithic Construction, Low Cost

14 +V

OUT

GND

–V

AD532

TOP VIEW

(Not to Scale)

AD532

TOP VIEW

(Not to Scale)

APPLICATIONS

Multiplication, Division, Squaring, Square Rooting

Algebraic Computation

Power Measurements

Instrumentation Applications

Available in Chip Form

GND

OUT

–V

NC = NO CONNECT

20 19

–V

AD532

TOP VIEW

15 NC

NC 7

(Not to Scale)

PRODUCT DESCRIPTION

GND

The AD532 is the first pretrimmed single chip monolithic multi-

plier/divider. It guarantees a maximum multiplying error of

±1.0% and a ±10 V output voltage without the need for any

external trimming resistors or output op amp. Because the

AD532 is internally trimmed, its simplicity of use provides

design engineers with an attractive alternative to modular multi-

pliers, and its monolithic construction provides significant ad-

vantages in size, reliability and economy. Further, the AD532

can be used as a direct replacement for other IC multipliers that

require external trim networks (such as the AD530).

10 11 12 13

NC = NO CONNECT

GUARANTEED PERFORMANCE OVER TEMPERATURE

The AD532J and AD532K are specified for maximum multi-

plying errors of ±2% and ±1% of full scale, respectively at

+25°C, and are rated for operation from 0°C to +70°C. The

AD532S has a maximum multiplying error of ±1% of full scale

at +25°C; it is also 100% tested to guarantee a maximum error

of ±4% at the extended operating temperature limits of –55°C

and +125°C. All devices are available in either the hermetically-

sealed TO-100 metal can, TO-116 ceramic DIP or LCC packages.

J, K and S grade chips are also available.

FLEXIBILITY OF OPERATION

The AD532 multiplies in four quadrants with a transfer func-

tion of (X₁– X₂)(Y₁– Y₂)/10 V, divides in two quadrants with

a 10 V Z/(X₁– X₂) transfer function, and square roots in one

quadrant with a transfer function of ±√10 V Z. In addition to

these basic functions, the differential X and Y inputs provide

significant operating flexibility both for algebraic computation and

transducer instrumentation applications. Transfer functions,

such as XY/10 V, (X²– Y²)/10 V, ±X²/10 V and 10 V Z/(X₁– X₂),

are easily attained and are extremely useful in many modulation

and function generation applications, as well as in trigonometric

calculations for airborne navigation and guidance applications,

where the monolithic construction and small size of the AD532

offer considerable system advantages. In addition, the high

CMRR (75 dB) of the differential inputs makes the AD532

especially well qualified for instrumentation applications, as it

can provide an output signal that is the product of two transducer-

generated input signals.

ADVANTAGES OF ON-THE-CHIP TRIMMING OF THE

MONOLITHIC AD532

1. True ratiometric trim for improved power supply rejection.

2. Reduced power requirements since no networks across sup-

plies are required.

3. More reliable since standard monolithic assembly techniques

can be used rather than more complex hybrid approaches.

4. High impedance X and Y inputs with negligible circuit

5. Differential X and Y inputs for noise rejection and additional

computational flexibility.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

12 3 4 5 6 7

下载PDF

与AD532J相关器件

型号	品牌	描述	获取价格	数据表
AD532JCHIP	ADI	Internally Trimmed Integrated Circuit Multiplier	获取价格
AD532JCHIPS	ADI	Internally Trimmed Integrated Circuit Multiplier	获取价格
AD532JD	ADI	Internally Trimmed Integrated Circuit Multiplier	获取价格
AD532JD/+	ADI	IC ANALOG MULTIPLIER OR DIVIDER, 1 MHz BAND WIDTH, CDIP14, SIDE BRAZED, CERAMIC, DIP-14, A	获取价格
AD532JD+	ADI	Internally Trimmed Integrated Circuit Multiplier	获取价格
AD532JDZ	ADI	Internally Trimmed Integrated Circuit Multiplier	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

AD532J

AD532J 技术参数

AD532J 数据手册

与AD532J相关器件

与AD532J相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD532J

AD532J 技术参数

AD532J 数据手册

与AD532J相关器件

与AD532J相关文章

您还可以找

您在本页遇到什么问题？