Datasheet > AD5316ARU-REEL7

AD5316ARU-REEL7

更新时间： 2024-02-09 18:13:29

品牌	Logo	应用领域
亚德诺 - ADI		转换器光电二极管
页数	文件大小	规格书
24页	528K
描述
2.5 V to 5.5 V, 400 Î¼A, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs

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技术参数
数据手册

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AD5316ARU-REEL7 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	TSSOP, TSSOP16,.25
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.59	最大模拟输出电压：	5.499 V
最小模拟输出电压：	0.001 V	转换器类型：	D/A CONVERTER
输入位码：	BINARY	输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e0
长度：	5 mm	最大线性误差 (EL)：	0.293%
湿度敏感等级：	1	位数：	10
功能数量：	1	端子数量：	16
最高工作温度：	105 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	240
电源：	3/5 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大稳定时间：	9 µs
标称安定时间 (tstl)：	7 µs	子类别：	Other Converters
最大压摆率：	0.9 mA	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	Base Number Matches：	1

AD5316ARU-REEL7 数据手册

AD5306/AD5316/AD5326

In asynchronous mode, the outputs are not updated at the same

However, if the master sends an ACK and continues clocking

SCL (no stop is sent), the DAC retransmits the same two bytes

of data on SDA. This allows continuous readback of data from

the selected DAC register.

time the input registers are written to. When

goes low,

LDAC

the DAC registers are updated with the contents of the input

registers.

POWER-DOWN MODE

Alternatively, the user can send a start followed by the address

with R/ = 1. In this case, the previously loaded pointer

settings are used and readback of data can start immediately.

The AD5306/AD5316/AD5326 have very low power consump-

tion, dissipating typically at 1.2 mW with a 3 V supply and

2.5 mW with a 5 V supply. Power consumption can be reduced

further when the DACs are not in use by putting them into

DOUBꢀE-BUFFERED INTERFACE

The AD5306/AD5316/AD5326 DACs have double-buffered

interfaces consisting of two banks of registers: input registers

and DAC registers. The input registers are connected directly to

the input shift register and the digital code is transferred to the

relevant input register on completion of a valid write sequence.

The DAC registers contain the digital code used by the resistor

strings.

power-down mode, which is selected by setting the

or by setting Bit 12 ( ) of the data-word to 0.

pin low

When the

pin is high and the

bit is set to 1, all DACs work

normally with a typical power consumption of 500 μA at 5 V

(400 μA at 3 V). In power-down mode, however, the supply

current falls to 300 nA at 5 V (90 nA at 3 V) when all DACs are

powered down. Not only does the supply current drop, but each

output stage is internally switched from the output of its ampli-

fier, making it open-circuit. This has the advantage that the

outputs are three-state while the part is in power-down mode

and provides a defined input condition for whatever is connected

to the output of the DAC amplifiers. The output stage is shown

in Figure 35.

Access to the DAC registers is controlled by the

pin.

LDAC

When

is high, the DAC registers are latched and the

LDAC

input registers can change state without affecting the contents of

the DAC registers. When is low, however, the DAC

LDAC

registers become transparent and the contents of the input

registers are transferred to them.

Double-buffering is useful if the user requires simultaneous

updating of all DAC outputs. The user may write to each of the

RESISTOR

STRING DAC

AMPLIFIER

OUT

input registers individually and then, by pulsing the

LDAC

input low, all outputs update simultaneously.

POWER-DOWN

CIRCUITRY

These parts contain an extra feature whereby a DAC register is

not updated unless its input register has been updated since the

Figure 35. Output Stage During Power-Down

last time that

was low. Normally, when

is low, the

LDAC

The bias generator, output amplifiers, resistor strings, and all

other associated linear circuitry are shut down when power-

down mode is activated. However, the contents of the registers

are unaffected when in power-down. In fact, it is possible to

load new data into the input registers and DAC registers during

DAC registers are filled with the contents of the input registers.

In the AD5306/AD5316/AD5326, the part updates the DAC

time the DAC register was updated, thereby removing

unnecessary digital crosstalk.

power-down. The DAC outputs update as soon as the

ꢀOAD DAC INPUT ꢀDAC

goes high or the

bit is reset to 1. The time to exit power-

down is typically 2.5 μs for V_DD= 5 V and 5 μs for V_DD= 3 V.

This is the time from the rising edge of the eighth SCL pulse or

transfers data from the input registers to the DAC

registers and, therefore, updates the outputs. The

LDAC

function enables double-buffering of the DAC data, GAIN,

LDAC

from the rising edge of

to when the output voltage deviates

from its power-down voltage (see Figure 23).

and BUF. There are two

modes: synchronous mode and

LDAC

asynchronous mode.

In synchronous mode, the DAC registers are updated after new

data is read in on the rising edge of the eighth SCL pulse.

LDAC

can be tied permanently low or pulsed as in Figure 2.

Rev. F | Page 19 of 24

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与AD5316ARU-REEL7相关器件

型号	品牌	描述	获取价格	数据表
AD5316ARUZ	ROCHESTER	SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO16, LEAD FREE, MO-153-AB, TSSOP-	获取价格
AD5316ARUZ	ADI	2.5 V to 5.5 V, 400 µA, 2-Wire Interface Quad Voltage Output 10-Bit DAC	获取价格
AD5316ARUZ1	ADI	2.5 V to 5.5 V, 400 Î¼A, 2-Wire Interface, Qu	获取价格
AD5316ARUZ-REEL7	ADI	IC SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO16, MO-153-AB, TSSOP-16, Digi	获取价格
AD5316BRU	ADI	2.5 V to 5.5 V, 400 Î¼A, 2-Wire Interface, Qu	获取价格
AD5316BRU	ROCHESTER	SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO16, MO-153-AB, TSSOP-16	获取价格

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