2.5 V to 5.5 V, 400 μA, 2-Wire Interface,
Quad Voltage Output, 8-/10-/12-Bit DACs
AD5306/AD5316/AD5326
FEATURES
FUNCTIONAꢀ BꢀOCK DIAGRAM
V
V
REF
A V B
REF
DD
AD5306: 4 buffered, 8-bit DACs in 16-lead TSSOP
A version: 1 ꢀSB INꢀ; B version: 0.625 ꢀSB INꢀ
AD5316: 4 buffered, 10-bit DACs in 16-lead TSSOP
A version: 4 ꢀSB INꢀ; B version: 2.5 ꢀSB INꢀ
AD5326: 4 buffered, 12-bit DACs in 16-lead TSSOP
A version: 16 ꢀSB INꢀ; B version: 10 ꢀSB INꢀ
ꢀow power operation: 400 μA @ 3 V, 500 μA @ 5 V
2-wire (I2C®-compatible) serial interface
2.5 V to 5.5 V power supply
AD5306/AD5316/AD5326
LDAC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
BUFFER
BUFFER
BUFFER
V
V
A
B
OUT
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
SCL
SDA
A1
OUT
INTERFACE
LOGIC
A0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
V
C
OUT
OUT
LDAC
INPUT
REGISTER
DAC
REGISTER
Guaranteed monotonic by design over all codes
Power-down to 90 nA @ 3 V, 300 nA @ 5 V (PD pin or bit)
Double-buffered input logic
STRING
DAC D
V
D
POWER-ON
RESET
POWER-DOWN
LOGIC
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 VREF
Power-on reset to 0 V
V
REF
D V C
REF
PD GND
Figure 1.
Simultaneous update of outputs (ꢀDAC pin)
Software clear facility
Data readback facility
GENERAꢀ DESCRIPTION
The AD5306/AD5316/AD53261 are quad 8-/10-/12-bit buffered
voltage output DACs in 16-lead TSSOP packages that operate
from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/μs. A 2-wire serial interface, which
operates at clock rates up to 400 kHz, is used. This interface is
SMBus-compatible at VDD < 3.6 V. Multiple devices can be
placed on the same bus.
On-chip rail-to-rail output buffer amplifiers
Temperature range −40°C to +105°C
APPꢀICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Each DAC has a separate reference input that can be configured
as buffered or unbuffered. The outputs of all DACs can be
Industrial process control
updated simultaneously using the asynchronous
input.
LDAC
The parts incorporate a power-on reset circuit that ensures the
DAC outputs power up to 0 V and remain there until a valid
write to the device takes place. The software clear function
clears all DACs to 0 V. The parts contain a power-down feature
that reduces the current consumption of the device to
300 nA @ 5 V (90 nA @ 3 V).
All three parts have the same pinout, which allows users to select
the amount of resolution appropriate for their application without
redesigning their circuit board.
1 Protected by U.S. Patent Numbers 5,969,657 and 5,684,481.
Rev. F
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