Datasheet > AD5305ARMZ1

AD5305ARMZ1

更新时间： 2022-04-22 01:54:01

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	565K
描述
2.5 V to 5.5 V, 500 muA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs

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AD5305ARMZ1 数据手册

AD5305/AD5315/AD5325

SCL

R/W

LSB

SDA

START

COND

ACK

AD53x5

MSB

ACK

AD53x5

ADDRESS BYTE

POINTER BYTE

MASTER

SCL

SDA

MSB

LSB

R/W

REPEATED

START

COND

ACK

AD53x5

ACK

MASTER

ADDRESS BYTE

DATA BYTE

MASTER

SCL

SDA

MSB

LSB

ACK

STOP

COND

LEAST SIGNIFICANT DATA BYTE

MASTER

NOTE: DATA BYTES ARE THE SAME AS THOSE IN THE WRITE SEQUENCE EXCEPT THAT DON’T CARES ARE READ BACK AS 0s.

Figure 34. Readback Sequence

These parts contain an extra feature whereby the DAC register

is not updated unless its input register has been updated since

DOUBꢀE-BUFFERED INTERFACE

The AD5305/AD5315/AD5325 DACs have double-buffered

interfaces consisting of two banks of registers—input registers

and DAC registers. The input register is directly connected to the

input shift register and the digital code is transferred to the relevant

input register on completion of a valid write sequence. The DAC

LDAC

the last time that

was brought low. Normally, when

LDAC

is brought low, the DAC registers are filled with the

contents of the input registers. In the case of the AD5305/AD5315/

AD5325, the part updates the DAC register only if the input

was updated, thereby removing unnecessary digital crosstalk.

LDAC

Access to the DAC register is controlled by the

bit. When

bit is set high, the DAC register is latched and,

therefore, the input register can change state without affecting

LDAC

POWER-DOWN MODES

LDAC

the

The AD5305/AD5315/AD5325 have very low power consumption,

dissipating typically 1.5 mW with a 3 V supply and 3 mW with

a 5 V supply. Power consumption can be further reduced when

the DACs are not in use by putting them into one of three

power-down modes, which are selected by Bit 15 and Bit 14

(PD1 and PD0) of the data byte. Table 8 shows how the state of

the bits corresponds to the mode of operation of the DAC.

the contents of the DAC register. However, when the

bit

is set low, the DAC register becomes transparent and the

contents of the input register are transferred to it.

This is useful if the user requires simultaneous updating of all

DAC outputs. The user can write to three of the input registers

LDAC

individually and then, by setting the

bit low when

Table 8. PD1/PD0 Operating Modes

writing to the remaining DAC input register, all outputs update

simultaneously.

PD1

PD0

Operating Mode

Normal Operation

Power-Down (1 kΩ load to GND)

Power-Down (100 kΩ load to GND)

Power-Down (three-state output)

Rev. G | Page 18 of 24

1...15 16 171819 20 21...24

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与AD5305ARMZ1相关器件

型号	品牌	描述	获取价格	数据表
AD5305ARMZ-REEL71	ADI	2.5 V to 5.5 V, 500 muA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs	获取价格
AD5305BRM	ADI	2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs	获取价格
AD5305BRM-REEL	ADI	2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs	获取价格
AD5305BRM-REEL7	ADI	2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs	获取价格
AD5305BRMZ	ADI	2.5 V to 5.5 V, 500 muA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs	获取价格
AD5305BRMZ1	ADI	2.5 V to 5.5 V, 500 Î¼A, 2-Wire Interface Int	获取价格

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