AD5304BRM

更新时间： 2024-01-07 02:58:32

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
15页	227K
描述
2.5 V to 5.5 V, 500 uA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead microSOIC

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AD5304BRM 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP10,.19,20	针数：	10
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.6
最大模拟输出电压：	5.499 V	最小模拟输出电压：	0.001 V
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	SERIAL	JESD-30 代码：	S-PDSO-G10
JESD-609代码：	e3	长度：	3 mm
最大线性误差 (EL)：	0.2441%	湿度敏感等级：	1
位数：	8	功能数量：	1
端子数量：	10	最高工作温度：	105 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP10,.19,20
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	3/5 V
认证状态：	Not Qualified	座面最大高度：	1.1 mm
最大稳定时间：	8 µs	标称安定时间 (tstl)：	6 µs
子类别：	Other Converters	最大压摆率：	0.9 mA
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3 mm
Base Number Matches：	1

AD5304BRM 数据手册

AD5304/AD5314/AD5324

FUNCTIONAL DESCRIPTION

DAC Reference Inputs

The AD5304/AD5314/AD5324 are quad resistor-string DACs

fabricated on a CMOS process with resolutions of 8, 10, and 12

bits respectively. Each contains four output buffer ampliﬁers and

is written to via a 3-wire serial interface. They operate from

single supplies of 2.5 V to 5.5 V and the output buffer ampliﬁers

provide rail-to-rail output swing with a slew rate of 0.7 V/µs. The

four DACs share a single reference input pin. The devices have

programmable power-down modes, in which all DACs may be

turned off completely with a high-impedance output.

There is a single reference input pin for the four DACs. The

reference input is unbuffered. The user can have a reference

voltage as low as 0.25 V and as high as V_DDsince there is no

restriction due to headroom and footroom of any reference

ampliﬁer.

It is recommended to use a buffered reference in the external

circuit (e.g., REF192). The input impedance is typically 45 kΩ.

Output Ampliﬁer

The output buffer ampliﬁer is capable of generating rail-to-rail

voltages on its output, which gives an output range of 0 V to V_DD

when the reference is V_DD. It is capable of driving a load of

Digital-to-Analog Section

The architecture of one DAC channel consists of a resistor-string

DAC followed by an output buffer ampliﬁer. The voltage at the

REFIN pin provides the reference voltage for the DAC. Figure

27 shows a block diagram of the DAC architecture. Since the

input coding to the DAC is straight binary, the ideal output

voltage is given by:

2 kΩ to GND or V_DD, in parallel with 500 pF to GND or V_DD

The source and sink capabilities of the output ampliﬁer can be

seen in the plot in Figure 14.

The slew rate is 0.7 V/µs with a half-scale settling time to

0.5 LSB (at 8 bits) of 6 µs.

V_REF× D

V_OUT

2^N

POWER-ON RESET

The AD5304/AD5314/AD5324 are provided with a power-on

reset function, so that they power up in a deﬁned state. The

power-on state is:

where

D = decimal equivalent of the binary code, which is loaded to the

DAC register;

– Normal operation.

– Output voltage set to 0 V.

0–255 for AD5304 (8 Bits)

0–1023 for AD5314 (10 Bits)

0–4095 for AD5324 (12 Bits)

Both input and DAC registers are ﬁlled with zeros and remain

so until a valid write sequence is made to the device. This is

particularly useful in applications where it is important to know

the state of the DAC outputs while the device is powering up.

N = DAC resolution

REFIN

SERIAL INTERFACE

INPUT

The AD5304/AD5314/AD5324 are controlled over a versatile,

3-wire serial interface, which operates at clock rates up to 30 MHz

and is compatible with SPI, QSPI, MICROWIRE, and DSP

interface standards.

DAC

RESISTOR

STRING

OUT

OUTPUT BUFFER

AMPLIFIER

Input Shift Register

Figure 27. DAC Channel Architecture

Resistor String

The input shift register is 16 bits wide. Data is loaded into the

device as a 16-bit word under the control of a serial clock input,

SCLK. The timing diagram for this operation is shown in Figure 1.

The 16-bit word consists of four control bits followed by 8, 10,

or 12 bits of DAC data, depending on the device type. Data

is loaded MSB ﬁrst (Bit 15) and the ﬁrst two bits determine

whether the data is for DAC A, DAC B, DAC C, or DAC D.

Bits 13 and 12 control the operating mode of the DAC. Bit 13 is

PD, which determines whether the part is in normal or power-

down mode. Bit 12 is LDAC, which controls when DAC registers

and outputs are updated.

The resistor string section is shown in Figure 28. It is simply a

string of resistors, each of value R. The digital code loaded to the

DAC register determines at which node on the string the voltage

is tapped off to be fed into the output ampliﬁer. The voltage is

tapped off by closing one of the switches connecting the string to

the ampliﬁer. Because it is a string of resistors, it is guaranteed

monotonic.

Table I. Address Bits for the AD53x4

TO OUTPUT

AMPLIFIER

DAC Addressed

DAC A

DAC B

DAC C

DAC D

Figure 28. Resistor String

REV. B

–9–

1...6 7 8910 11 12...15

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与AD5304BRM相关器件

型号	品牌	描述	获取价格	数据表
AD5304BRM-REEL	ADI	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output	获取价格
AD5304BRM-REEL7	ADI	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output	获取价格
AD5304BRMZ	ADI	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output	获取价格
AD5304BRMZ-REEL	ADI	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output	获取价格
AD5304BRMZ-REEL7	ADI	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output	获取价格
AD5305	ADI	2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs	获取价格

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