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AD5302BRMZ-REEL

更新时间： 2024-02-15 18:39:06
品牌 Logo 应用领域
亚德诺 - ADI 转换器光电二极管
页数 文件大小 规格书
24页 1044K
描述
2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs

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中文翻译

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AD5302BRMZ-REEL 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：10
Reach Compliance Code：unknown风险等级：5.7
Is Samacsys：N最大模拟输出电压：5.499 V
最小模拟输出电压：0.001 V转换器类型：D/A CONVERTER
输入位码：BINARY输入格式：SERIAL
JESD-30 代码：S-PDSO-G10JESD-609代码：e3
长度：3 mm最大线性误差 (EL)：0.1953%
湿度敏感等级：1位数：8
功能数量：1端子数量：10
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：SQUARE封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：COMMERCIAL
座面最大高度：1.1 mm标称安定时间 (tstl)：6 µs
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：3 mm
Base Number Matches：1

AD5302BRMZ-REEL 数据手册

 浏览型号AD5302BRMZ-REEL的Datasheet PDF文件第5页浏览型号AD5302BRMZ-REEL的Datasheet PDF文件第6页浏览型号AD5302BRMZ-REEL的Datasheet PDF文件第7页浏览型号AD5302BRMZ-REEL的Datasheet PDF文件第9页浏览型号AD5302BRMZ-REEL的Datasheet PDF文件第10页浏览型号AD5302BRMZ-REEL的Datasheet PDF文件第11页 
AD5302/AD5312/AD5322  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
LDAC  
1
2
3
4
5
10 GND  
AD5302/  
AD5312/  
V
9
8
7
6
DIN  
DD  
V
B
A
SCLK  
SYNC  
REF  
AD5322  
V
TOP VIEW  
REF  
OUT  
(Not to Scale)  
V
A
V
B
OUT  
Figure 5. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin No.  
Mnemonic Description  
1
LDAC  
Active Low Control Input. This pin transfers the contents of the input registers to their respective DAC registers.  
Pulsing LDAC low allows either or both DAC registers to be updated if the input registers have new data. This  
allows simultaneous updating of both DAC outputs.  
2
3
VDD  
VREF  
Power Supply Input. The parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.  
B
Reference Input Pin for DAC B. This is the reference for DAC B. It can be configured as a buffered or an  
unbuffered input, depending on the BUF bit in the control word of DAC B. It has an input range of 0 V to VDD in  
unbuffered mode and 1 V to VDD in buffered mode.  
4
VREF  
A
Reference Input Pin for DAC A. This is the reference for DAC A. It can be configured as a buffered or an  
unbuffered input depending on the BUF bit in the control word of DAC A. It has an input range of 0 V to VDD in  
unbuffered mode and 1 V to VDD in buffered mode.  
5
ꢀ
7
VOUT  
VOUT  
SYNC  
A
B
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.  
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.  
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it  
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling  
edges of the following 1ꢀ clocks. If SYNC is taken high before the 1ꢀth falling edge, the rising edge of SYNC acts  
as an interrupt and the write sequence is ignored by the device.  
8
SCLK  
DIN  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data  
can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.  
Serial Data Input. This device has a 1ꢀ-bit input shift register. Data is clocked into the register on the falling  
edge of the serial clock input. The DIN input buffer is powered down after each write cycle.  
9
10  
GND  
Ground Reference Point for All Circuitry on the Part.  
Rev. D | Page 8 of 24  
 
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中文翻译

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AD5302BRMZ-REEL 替代型号

型号 品牌 替代类型 描述 数据表
AD5302BRMZ-REEL7 ADI

完全替代

 		2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail, V
AD5302BRM-REEL7 ADI

完全替代

 		2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail, V

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