Datasheet > 转换器 > 数模转换器> AD5300BRTZ-REEL7

AD5300BRTZ-REEL7

更新时间： 2024-01-11 12:57:32

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器光电二极管
页数	文件大小	规格书
12页	202K
描述
+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23

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技术参数
数据手册

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AD5300BRTZ-REEL7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	LSSOP,	针数：	6
Reach Compliance Code：	unknown	风险等级：	5.67
最大模拟输出电压：	5.5 V	最小模拟输出电压：
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	SERIAL	JESD-30 代码：	R-PDSO-G6
JESD-609代码：	e3	长度：	2.9 mm
最大线性误差 (EL)：	0.3906%	湿度敏感等级：	1
位数：	8	功能数量：	1
端子数量：	6	最高工作温度：	105 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL	座面最大高度：	1.45 mm
标称安定时间 (tstl)：	4 µs	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.95 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	1.6 mm	Base Number Matches：	1

AD5300BRTZ-REEL7 数据手册

浏览型号AD5300BRTZ-REEL7的Datasheet PDF文件第10页

AD5300

SCLK

SYNC

DB15

DB0

DB15

DB0

DIN

VALID WRITE SEQUENCE, OUTPUT UPDATES

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 16 FALLING EDGE

ON THE 16 FALLING EDGE

Figure 23. SYNC Interrupt Facility

SYNC Interrupt

In a normal write sequence, the SYNC line is kept low for at

least 16 falling edges of SCLK and the DAC is updated on the

16th falling edge. However, if SYNC is brought high before the

16th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as

invalid; neither an update of the DAC register contents or a

change in the operating mode occurs—see Figure 23.

RESISTOR

AMPLIFIER

STRING DAC

OUT

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

Power-On Reset

The AD5300 contains a power-on reset circuit that controls the

output voltage during power-up. The DAC register is filled with

zeros and the output voltage is 0 V. It remains there until

a valid write sequence is made to the DAC. This is useful in

applications where it is important to know the state of the out-

put of the DAC while it is in the process of powering up.

Figure 24. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and

other associated linear circuitry are all shut down when the

power-down mode is activated. However, the contents of the

DAC register are unaffected when in power-down. The time to

exit power-down is typically 2.5 µs for V_DD= 5 V and 5 µs for

V_DD= 3 V (see Figure 18).

Power-Down Modes

The AD5300 contains four separate modes of operation. These

modes are software programmable by setting two bits (DB13

and DB12) in the control register. Table I shows how the state

of the bits corresponds to the mode of operation of the device.

MICROPROCESSOR INTERFACING

AD5300 to ADSP-2101/ADSP-2103 Interface

Figure 25 shows a serial interface between the AD5300 and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set up to operate in the SPORT transmit alternate framing

mode. The ADSP-2101/ADSP-2103 SPORT is programmed

through the SPORT control register and should be configured

as follows: internal clock operation, active low framing, 16-bit

word length. Transmission is initiated by writing a word to the

Tx register after the SPORT has been enabled.

Table I. Modes of Operation for the AD5300

DB13

DB12

Operating Mode

Normal Operation

Power-Down Modes

1 kΩ to GND

100 kΩ to GND

Three-State

ADSP-2101/

ADSP-2103*

AD5300*

When both bits are set to 0, the part works normally with its

normal power consumption of 140 µA at 5 V. However, for the

three power-down modes, the supply current falls to 200 nA at

5 V (50 nA at 3 V). Not only does the supply current fall but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has an

advantage: the output impedance of the part is known while the

part is in power-down mode. There are three different options.

The output is connected internally to GND through a 1 kΩ resis-

tor or a 100 kΩ resistor, or it is left open-circuited (three-stated).

The output stage is illustrated in Figure 24.

SYNC

DIN

TFS

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 25. AD5300 to ADSP-2101/ADSP-2103 Interface

REV. C

–9–

1...6 7 8910 11 12

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与AD5300BRTZ-REEL7相关器件

型号	品牌	描述	获取价格	数据表
AD5300WBRTZ-RL7	ADI	2.7 V to 5.5 V, 140 muA, Rail-to-Rail Output 8-Bit DAC in a SOT-23	获取价格
AD5301	ADI	+2.5 V to +5.5 V, 120 uA, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACs	获取价格
AD5301_07	ADI	2.5 V to 5.5 V, 120 Î¼A, 2-Wire Interface, Vo	获取价格
AD5301_16	ADI	2-Wire Interface, Voltage-Output 8-/10-/12-Bit DACs	获取价格
AD5301BRM	ADI	+2.5 V to +5.5 V, 120 uA, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACs	获取价格
AD5301BRM-REEL	ADI	2.5 V to 5.5 V, 120 Î¼A, 2-Wire Interface, Vo	获取价格

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