AD53020

更新时间： 2024-11-18 22:38:59

品牌	Logo	应用领域
亚德诺 - ADI		延迟线逻辑集成电路
页数	文件大小	规格书
4页	74K
描述
Four Channel ECL Delay Line

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AD53020 数据手册

Four Channel ECL Delay Line

AD53020

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Four Delay Lines with the Ability to Independently

Adjust All Edges

GND

Pin Compatible and Functionally Equivalent with the

BT624

Reduced Power Dissipation

VWIDTH1

OUT1

AD53020

IN1, IN1

44-Lead PLCC Package with Internal Heat Spreader

OUT1

APPLICATIONS

VDELAY1

VWIDTH2

Automatic Test Equipment

Semiconductor Test Systems

Board Test Systems

OUT2

IN2, IN2

Clocked ECL Circuits

OUT2

DRVMODE

VDELAY2

VWIDTH3

OUT3

IN3, IN3

OUT3

PRODUCT DESCRIPTION

VDELAY3

VWIDTH4

The AD53020 is a four-channel delay line designed for use in

automatic test equipment and digital logic systems. High speed

bipolar transistors and a 44-lead plastic PLCC package with

internal heat spreader provide high frequency performance at a

minimum of space, cost and power dissipation.

OUT4

IN4, IN4

OUT4

VDELAY4

Featuring full pin compatibility and functional equivalence to

the BT624, the AD53020 offers independent analog control of

positive and negative edges with five delay ranges. The AD53020

offers attractive performance with optimized power dissipation

and linear delay vs. program voltage control. This device is also

very stable over operating conditions and has very low jitter.

COMP1

COMP2

REXT1

REXT2

Digital inputs are ECL compatible. They can either be pro-

vided independently for each channel (IN1, IN1 through IN4,

IN4), or fanned out to all channels from Channel 2 (IN2,

IN2). The choice of these two options is made by setting the

DRVMODE input, with ECL Logic 0 providing four indepen-

dent channels, and ECL Logic 1 enabling a logical OR function

between each channel and the Channel Number 2.

The delay is programmed through the VDELAY and VWIDTH

pins for each channel. The acceptable range is –1.3 V to –0.1 V,

representing the longest and the shortest delays provided by the

device. An 0.01 µF ceramic capacitor to ground is recom-

mended for each input. The bias current for each input is fixed

by an internal current mirror. The value of the bias current is

set by the external resistor at REXT1. A 1.3 kΩ resistor to

ground at this pin establishes 1 mA bias in each input. The

nominal voltage at the REXT1 pin is –1.3 V.

For maximum timing accuracy, differential signals are recom-

mended for use with the digital inputs. However, single-ended

operation is also supported and it is facilitated through the use

of the V_BBmidpoint level generated on-chip. To make use of

this feature, connect the V_BBoutput to the inverting input of

each channel. It is also advisable, when using the V_BBoutput,

to decouple this signal with a 0.1 µF ceramic capacitor to ground.

The VDELAY affects both the positive and negative edges in all

modes. The VWIDTH is an additional delay adjustment that is

active in Modes 2, 3 and 5. VWIDTH has no effect in Modes 0

and 1. For Modes 2 and 3, the effect of the VWIDTH adjust-

ment is to increase or decrease the delay of the negative edge

relative to the positive edge. In Mode 5, the total delay for both

positive and negative edges is set by the combination of VDELAY

and VWIDTH.

The outputs of the AD53020 are ECL compatible and should

be terminated by 50 Ω to –2.0 V at the inputs of the gates

they drive.

(continued on page 4)

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

12 3 4

中文翻译

下载PDF

与AD53020相关器件

型号	品牌	获取价格	描述	数据表
AD53020JP	ADI	获取价格	IC ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQCC44, PLASTIC, LCC-44, Delay Line
AD5302ARM	ADI	获取价格	2.5 V to 5.5 V, 230 Î¼A, Dual Rail-to-Rail, V
AD5302ARM	ROCHESTER	获取价格	SERIAL INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, PDSO10, MO-187BA, MSOP-10
AD5302ARM-REEL	ADI	获取价格	IC SERIAL INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, PDSO10, MO-187BA, MSOP-10, Digital
AD5302ARM-REEL7	ADI	获取价格	2.5 V to 5.5 V, 230 Î¼A, Dual Rail-to-Rail, V
AD5302ARM-REEL7	ROCHESTER	获取价格	SERIAL INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, PDSO10, MO-187BA, MSOP-10
AD5302ARMZ	ADI	获取价格	2.5 V to 5.5 V, 230 Î¼A, Dual Rail-to-Rail, V
AD5302ARMZ	ROCHESTER	获取价格	SERIAL INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, PDSO10, ROHS COMPLIANT, MO-187BA, MSO
AD5302ARMZ-REEL	ADI	获取价格	2.5 V to 5.5 V, 230 Î¼A, Dual Rail-to-Rail, V
AD5302ARMZ-REEL7	ADI	获取价格	2.5 V to 5.5 V, 230 Î¼A, Dual Rail-to-Rail, V

与AD53020相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

23
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

15
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

45
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

45

产品中心

服务支持

精选活动

关于我们

帮助中心

AD53020

AD53020 数据手册

与AD53020相关器件

与AD53020相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD53020

AD53020 数据手册

与AD53020相关器件

与AD53020相关文章

您还可以找

您在本页遇到什么问题？