AD53020

更新时间： 2024-01-24 02:30:52

品牌	Logo	应用领域
亚德诺 - ADI		延迟线逻辑集成电路
页数	文件大小	规格书
4页	74K
描述
Four Channel ECL Delay Line

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AD53020 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	PLASTIC, LCC-44
针数：	44	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.85	JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e0	长度：	16.585 mm
逻辑集成电路类型：	ACTIVE DELAY LINE	功能数量：	1
抽头/阶步数：		端子数量：	44
最高工作温度：	70 °C	最低工作温度：	-55 °C
输出阻抗标称值（Z0）：	50 Ω	输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	4.57 mm	表面贴装：	YES
技术：	ECL	温度等级：	OTHER
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	总延迟标称（td）：	44.5 ns
宽度：	16.585 mm	Base Number Matches：	1

AD53020 数据手册

Four Channel ECL Delay Line

AD53020

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Four Delay Lines with the Ability to Independently

Adjust All Edges

GND

Pin Compatible and Functionally Equivalent with the

BT624

Reduced Power Dissipation

VWIDTH1

OUT1

AD53020

IN1, IN1

44-Lead PLCC Package with Internal Heat Spreader

OUT1

APPLICATIONS

VDELAY1

VWIDTH2

Automatic Test Equipment

Semiconductor Test Systems

Board Test Systems

OUT2

IN2, IN2

Clocked ECL Circuits

OUT2

DRVMODE

VDELAY2

VWIDTH3

OUT3

IN3, IN3

OUT3

PRODUCT DESCRIPTION

VDELAY3

VWIDTH4

The AD53020 is a four-channel delay line designed for use in

automatic test equipment and digital logic systems. High speed

bipolar transistors and a 44-lead plastic PLCC package with

internal heat spreader provide high frequency performance at a

minimum of space, cost and power dissipation.

OUT4

IN4, IN4

OUT4

VDELAY4

Featuring full pin compatibility and functional equivalence to

the BT624, the AD53020 offers independent analog control of

positive and negative edges with five delay ranges. The AD53020

offers attractive performance with optimized power dissipation

and linear delay vs. program voltage control. This device is also

very stable over operating conditions and has very low jitter.

COMP1

COMP2

REXT1

REXT2

Digital inputs are ECL compatible. They can either be pro-

vided independently for each channel (IN1, IN1 through IN4,

IN4), or fanned out to all channels from Channel 2 (IN2,

IN2). The choice of these two options is made by setting the

DRVMODE input, with ECL Logic 0 providing four indepen-

dent channels, and ECL Logic 1 enabling a logical OR function

between each channel and the Channel Number 2.

The delay is programmed through the VDELAY and VWIDTH

pins for each channel. The acceptable range is –1.3 V to –0.1 V,

representing the longest and the shortest delays provided by the

device. An 0.01 µF ceramic capacitor to ground is recom-

mended for each input. The bias current for each input is fixed

by an internal current mirror. The value of the bias current is

set by the external resistor at REXT1. A 1.3 kΩ resistor to

ground at this pin establishes 1 mA bias in each input. The

nominal voltage at the REXT1 pin is –1.3 V.

For maximum timing accuracy, differential signals are recom-

mended for use with the digital inputs. However, single-ended

operation is also supported and it is facilitated through the use

of the V_BBmidpoint level generated on-chip. To make use of

this feature, connect the V_BBoutput to the inverting input of

each channel. It is also advisable, when using the V_BBoutput,

to decouple this signal with a 0.1 µF ceramic capacitor to ground.

The VDELAY affects both the positive and negative edges in all

modes. The VWIDTH is an additional delay adjustment that is

active in Modes 2, 3 and 5. VWIDTH has no effect in Modes 0

and 1. For Modes 2 and 3, the effect of the VWIDTH adjust-

ment is to increase or decrease the delay of the negative edge

relative to the positive edge. In Mode 5, the total delay for both

positive and negative edges is set by the combination of VDELAY

and VWIDTH.

The outputs of the AD53020 are ECL compatible and should

be terminated by 50 Ω to –2.0 V at the inputs of the gates

they drive.

(continued on page 4)

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

12 3 4

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