AD5300BRM-REEL

更新时间： 2024-01-01 03:58:25

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器光电二极管
页数	文件大小	规格书
12页	202K
描述
+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23

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技术参数
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替代型号

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AD5300BRM-REEL 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	LSSOP, TSOP6,.11,37	针数：	6
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.31
最大模拟输出电压：	5.5 V	最小模拟输出电压：
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	SERIAL	JESD-30 代码：	R-PDSO-G6
JESD-609代码：	e3	长度：	2.9 mm
最大线性误差 (EL)：	0.3906%	湿度敏感等级：	1
位数：	8	功能数量：	1
端子数量：	6	最高工作温度：	105 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP	封装等效代码：	TSOP6,.11,37
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	3/5 V
认证状态：	Not Qualified	座面最大高度：	1.45 mm
最大稳定时间：	6 µs	标称安定时间 (tstl)：	4 µs
子类别：	Other Converters	最大压摆率：	0.25 mA
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.95 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	1.6 mm
Base Number Matches：	1

AD5300BRM-REEL 数据手册

AD5300

GENERAL DESCRIPTION

D/A Section

Output Amplifier

The AD5300 DAC is fabricated on a CMOS process. The archi-

tecture consists of a string DAC followed by an output buffer

amplifier. Since there is no reference input pin, the power

supply (V_DD) acts as the reference. Figure 20 shows a block

diagram of the DAC architecture.

The output buffer amplifier is capable of generating rail-to-rail

voltages on its output, which gives an output range of 0 V to

V_DD. It is capable of driving a load of 2 kΩ in parallel with

1000 pF to GND. The source and sink capabilities of the output

amplifier can be seen in Figures 8 and 9. The slew rate is 1 V/µs

with a half-scale settling time of 4 µs with the output loaded.

SERIAL INTERFACE

REF (+)

The AD5300 has a 3-wire serial interface (SYNC, SCLK, and

DIN), which is compatible with SPI, QSPI, and MICROWIRE

interface standards as well as most DSPs. See Figure 1 for a

timing diagram of a typical write sequence.

RESISTOR

STRING

DAC REGISTER

OUT

REF (–)

OUTPUT

AMPLIFIER

GND

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 16-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 30 MHz, making the AD5300 compatible with high speed

DSPs. On the 16th falling clock edge, the last data bit is clocked

in and the programmed function is executed (i.e., a change in

DAC register contents and/or a change in the mode of operation).

At this stage, the SYNC line may be kept low or be brought

high. In either case, it must be brought high for a minimum of

33 ns (V_DD= 3.6 V to 5.5 V) or 50 ns (V_DD= 2.7 V to 3.6 V)

before the next write sequence so that a falling edge of SYNC

can initiate the next write sequence. Since the SYNC buffer

Figure 20. DAC Architecture

Since the input coding to the DAC is straight binary, the ideal

output voltage is given by





256

V_OUT=V_DD









where D = decimal equivalent of the binary code that is loaded

to the DAC register; D can range from 0 to 255.

Resistor String

The resistor string section is shown in Figure 21. It is simply a

string of resistors, each of value R. The code loaded to the

DAC register determines at which node on the string the voltage

is tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. Because it is a string of resistors, it is guaran-

teed monotonic.

draws more current when V_IN= 2.4 V than it does when V_IN

0.8 V, SYNC should be idled low between write sequences for

even lower power operation of the part. As previously men-

tioned, however, it must be brought high again just before the

next write sequence.

Input Shift Register

The input shift register is 16 bits wide (see Figure 22). The first

two bits are Don’t Cares. The next two are control bits that

control which mode of operation the part is in (normal mode or

any one of three power-down modes). There is a more complete

description of the various modes in the Power-Down Modes

section. The next eight bits are the data bits. These are transferred

to the DAC register on the 16th falling edge of SCLK. Finally, the

last four bits are Don’t Cares.

TO OUTPUT

AMPLIFIER

Figure 21. Resistor String

DB15 (MSB)

DB0 (LSB)

PD1

PD0

DATA BITS

NORMAL OPERATION

1k⍀ TO GND

100k⍀ TO GND

POWER-DOWN MODES

THREE-STATE

Figure 22. Input Register Contents

–8–

REV. C

1...5 6 789 10 11 12

中文翻译

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AD5300BRM-REEL 替代型号

型号	品牌	替代类型	描述	数据表
AD5300BRMZ-REEL7	ADI	完全替代	2.7 V to 5.5 V, 140 muA, Rail-to-Rail Output 8-Bit DAC in a SOT-23
AD5300BRM	ADI	完全替代	+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23

与AD5300BRM-REEL相关器件

型号	品牌	描述	获取价格	数据表
AD5300BRM-REEL7	ADI	+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23	获取价格
AD5300BRMZ	ADI	2.7 V to 5.5 V, 140 muA, Rail-to-Rail Output 8-Bit DAC in a SOT-23	获取价格
AD5300BRMZ-REEL	ADI	2.7 V to 5.5 V, 140 muA, Rail-to-Rail Output 8-Bit DAC in a SOT-23	获取价格
AD5300BRMZ-REEL7	ADI	2.7 V to 5.5 V, 140 muA, Rail-to-Rail Output 8-Bit DAC in a SOT-23	获取价格
AD5300BRT	ADI	+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23	获取价格
AD5300BRT-500RL7	ADI	+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23	获取价格

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