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AD5258BRMZ50-R7 PDF预览

AD5258BRMZ50-R7

更新时间： 2024-01-08 12:24:33
品牌 Logo 应用领域
亚德诺 - ADI 电位器
页数 文件大小 规格书
24页 534K
描述
Nonvolatile, I2C-Compatible 64-Position, Digital Potentiometer

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AD5258BRMZ50-R7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP10,.19,20针数：10
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.32
其他特性：NONVOLATILE MEMORY标称带宽：0.19 kHz
控制接口：2-WIRE SERIAL转换器类型：DIGITAL POTENTIOMETER
JESD-30 代码：S-PDSO-G10JESD-609代码：e3
长度：3 mm湿度敏感等级：1
功能数量：1位置数：64
端子数量：10最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP10,.19,20
封装形状：SQUARE封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified电阻定律：LINEAR
最大电阻容差：30%最大电阻器端电压：5.5 V
最小电阻器端电压：座面最大高度：1.1 mm
子类别：Digital Potentiometers标称供电电压：3 V
表面贴装：YES标称温度系数：200 ppm/ °C
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
标称总电阻：50000 Ω宽度：3 mm
Base Number Matches：1

AD5258BRMZ50-R7 数据手册

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Data Sheet  
AD5258  
of powering VA, VB, VW and the digital inputs is not important  
ESD PROTECTION OF DIGITAL PINS AND  
RESISTOR TERMINALS  
as long as they are powered after GND, VDD, and VLOGIC  
.
The AD5258 VDD, VLOGIC, and GND power supplies define the  
boundary conditions for proper 3-terminal and digital input  
operation. Supply signals present on Terminal A, Terminal B,  
and Terminal W that exceed VDD or GND are clamped by the  
internal forward-biased ESD protection diodes (see Figure 40).  
Digital Input SCL and Digital Input SDA are clamped by ESD  
protection diodes with respect to VLOGIC and GND as shown in  
Figure 41.  
LAYOUT AND POWER SUPPLY BYPASSING  
It is good practice to employ compact, minimum lead length  
layout design. The leads to the inputs should be as direct as  
possible with minimum conductor length. Ground paths  
should have low resistance and low inductance.  
Similarly, it is also good practice to bypass the power supplies  
with quality capacitors for optimum stability. Supply leads to  
the device should be bypassed with disc or chip ceramic capaci-  
tors of 0.01 µF to 0.1 µF. In addition, low ESR 1 µF to 10 µF  
tantalum or electrolytic capacitors should be applied at the  
supplies to minimize any transient disturbance and low fre-  
quency ripple (see Figure 42). As well, the digital ground  
should be joined remotely to the analog ground at one point  
to minimize the ground bounce.  
V
DD  
A
W
B
GND  
Figure 40. Maximum Terminal Voltages Set by VDD and GND  
V
V
DD  
DD  
+
C2  
10µF  
C1  
0.1µF  
V
LOGIC  
AD5258  
SCL  
SDA  
GND  
GND  
Figure 42. Power Supply Bypassing  
Figure 41. Maximum Terminal Voltages Set by VLOGIC and GND  
MULTIPLE DEVICES ON ONE BUS  
POWER-UP SEQUENCE  
The AD5258 has two configurable address pins, AD0 and AD1.  
The state of these two pins is registered upon power-up and  
decoded into a corresponding I2C-compatible 7-bit address (see  
Table 5). This allows up to four devices on the bus to be written  
to or read from independently.  
Because the ESD protection diodes limit the voltage compliance  
at Terminal A, Terminal B, and Terminal W (see Figure 40), it is  
important to power GND/VDD/VLOGIC before applying any volt-  
age to Terminal A, Terminal B, and Terminal W; otherwise, the  
diode is forward-biased such that VDD and VLOGIC are powered  
unintentionally and may affect the user’s circuit. The ideal  
power-up sequence is in the following order: GND, VDD  
,
V
LOGIC, digital inputs, and then VA, VB, VW. The relative order  
Rev. D | Page 19 of 24  
 
 
 
 
 
 
 
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