AD5255BRU250

更新时间： 2024-02-03 15:22:58

品牌	Logo	应用领域
亚德诺 - ADI		电位器存储
页数	文件大小	规格书
20页	824K
描述
3-Channel Digital Potentiometer with Nonvolatile Memory

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数据手册

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AD5255BRU250 数据手册

AD5255

ELECTRICAL CHARACTERISTICS

Single supply: V_DD= 2.7 V to 5.5 V and −40°C < T_A< +85°C, unless otherwise noted.

Dual supply: V_DD= +2.25 V or +2.75 V, V_SS= −2.25 V or −2.75 V and −40°C < T_A< +85°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS,

RHEOSTAT MODE

Resistor Differential Nonlinearity²

R-DNL

R_WB, 7-bit channel

R_WB, 9-bit channels

−0.75

−2.5

+0.75

+2.5

LSB

Resistor Integral Nonlinearity²

R-INL

(∆R_WB/R_WB)/∆T × 10⁶

R_WB, 7-bit channel

R_WB, 9-bit channels, V_DD= 5.5 V

R_WB, 9-bit channels, V_DD= 2.7 V

−0.5

−2.0

−4.0

+0.5

+2.0

+4.0

LSB

ppm/°C

Ω

Resistance Temperature Coefficent

Wiper Resistance

R_W

V_DD= 5 V, I_W= 1 V/R_WB

V_DD= 3 V, I_W= 1 V/R_WB

Ch 1 and 2 R_WB, Dx = 0x1FF

Dx = 0x3FF

100

250

0.1

150

400

Channel Resistance Matching

Nominal Resistor Tolerance

∆R_AB1/∆R_AB2

∆R_AB/R_AB

−15

+15

DC CHARACTERISTICS,

POTENTIOMETER DIVIDER MODE

Differential Nonlinearity³

DNL

7-bit channel

9-bit channels

−0.5

−2.0

+0.5

+2.0

LSB

Integral Nonlinearity³

INL

7-bit channel

9-bit channels

Code = half-scale

−0.5

−2.0

+0.5

+2.0

LSB

ppm/°C

Voltage Divider Temperature

Coefficent

(∆V_W/V_W)/∆T × 10⁶

Full-Scale Error

V_WFSE

V_WZSE

7-bit channel/9-bit channel,

code = full-scale

7-bit channel/9-bit channel,

code = zero-scale

−1/−2.75

0/0

LSB

Zero-Scale Error

1/2.0

RESISTOR TERMINALS

Terminal Voltage Range⁴

Capacitance⁵Ax, Bx

V_{A, B, W}

C_A,B

V_SS

V_DD

f = 1 kHz, measured to GND,

code = half-scale

f = 1 kHz, measured to GND,

code = half-scale

Capacitance⁵Wx

C_W

I_CM

Common-Mode Leakage Current ^{5, 8}

DIGITAL INPUTS AND OUTPUTS

Input Logic High

V_W= V_DD/2

0.01

µA

V_IH

V_IL

V_DD= 5 V, V_SS= 0 V

V_DD/V_SS= +2.7 V/0 V or

V_DD/V_SS= 2.5 V

V_DD= 5 V, V_SS= 0 V

V_DD/V_SS= +2.7 V/0 V or

V_DD/V_SS= 2.5 V

2.4

2.1

Input Logic Low

0.8

0.6

Output Logic High (SDA)

Output Logic Low

V_OH

V_OL

R_PULL-UP= 2.2 kΩ to V_DD= 5 V,

V_SS= 0 V

R_PULL-UP= 2.2 kΩ to V_DD= 5 V,

V_SS= 0 V

4.9

0.4

WP Leakage Current

A0 Leakage Current

I_WP

I_A0

WP = V_DD

µA

A0 = GND

Rev. 0 | Page 3 of 20

1 234 5 6 7...20

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