AD5255BRU250

更新时间： 2024-01-21 06:55:39

品牌	Logo	应用领域
亚德诺 - ADI		电位器存储
页数	文件大小	规格书
20页	824K
描述
3-Channel Digital Potentiometer with Nonvolatile Memory

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数据手册

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AD5255BRU250 数据手册

AD5255

INTERFACE DESCRIPTIONS

I²C INTERFACE

All control and access to both EEPROM memory and the RDAC

registers are conducted via a standard 2-wire I²C interface.

Figure 2 shows the timing characteristics of the I²C bus.

Figure 16 and Figure 17 illustrate standard transmit and receive

bus signals in the I²C interface.

These figures use the following legend:

From master to slave

From slave to master

S = Start condition

P = Stop condition

A = Acknowledge (SDA low)

= Not acknowledge (SDA high)

R/ = Read enable at high and write enable at low

SLAVE ADDRESS

R/W

DATA

A/A

DATA TRANSFERRED

(N BYTES + ACKNOWLEDGE)

0 = WRITE

Figure 16. I²C—Master Transmitting Data to Slave

SLAVE ADDRESS

R/W

DATA

DATA TRANSFERRED

(N BYTES + ACKNOWLEDGE

1 = WRITE

Figure 17. I²C—Master Reading Data from Slave

SLAVE ADDRESS

R/W

DATA

A/A

SLAVE ADDRESS

R/W

DATA

A/A

(N BYTES + ACKNOWLEDGE)

READ OR WRITE

REPEATED START

READ OR WRITE

DIRECTION OF TRANSFER MAY

CHANGE AT THIS POINT

Figure 18. Combined Transmit/Read

Rev. 0 | Page 10 of 20

1...7 8 91011 12 13...20

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