5秒后页面跳转
捷配首页

Datasheet > AD5248BRMZ100
AD5248BRMZ100 PDF预览

AD5248BRMZ100

更新时间： 2024-01-05 05:43:21
品牌 Logo 应用领域
亚德诺 - ADI 电位器
页数 文件大小 规格书
20页 803K
描述
Dual, 256-Position, I2C-Compatible Digital Potentiometers

阅读下载

获取价格

AD5248BRMZ100 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP10,.19,20针数：10
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.12
其他特性：IT ALSO OPERATES AT 5 V SUPPLY标称带宽：0.04 kHz
控制接口：2-WIRE SERIAL转换器类型：DIGITAL POTENTIOMETER
JESD-30 代码：S-PDSO-G10JESD-609代码：e3
长度：3 mm湿度敏感等级：1
功能数量：2位置数：256
端子数量：10最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP10,.19,20
封装形状：SQUARE封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified电阻定律：LINEAR
最大电阻容差：20%最大电阻器端电压：5.5 V
最小电阻器端电压：座面最大高度：1.1 mm
子类别：Digital Potentiometers标称供电电压：3 V
表面贴装：YES标称温度系数：35 ppm/ °C
温度等级：AUTOMOTIVE端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
标称总电阻：100000 Ω宽度：3 mm
Base Number Matches：1

AD5248BRMZ100 数据手册

 浏览型号AD5248BRMZ100的Datasheet PDF文件第11页浏览型号AD5248BRMZ100的Datasheet PDF文件第12页浏览型号AD5248BRMZ100的Datasheet PDF文件第13页浏览型号AD5248BRMZ100的Datasheet PDF文件第15页浏览型号AD5248BRMZ100的Datasheet PDF文件第16页浏览型号AD5248BRMZ100的Datasheet PDF文件第17页 
AD5243/AD5248  
Data Sheet  
PROGRAMMING THE POTENTIOMETER DIVIDER  
TERMINAL VOLTAGE OPERATING RANGE  
Voltage Output Operation  
The AD5243/AD5248 VDD and GND power supply defines the  
boundary conditions for proper 3-terminal digital potentiometer  
operation. Supply signals present on the A, B, and W terminals  
that exceed VDD or GND are clamped by the internal forward-  
biased diodes (see Figure 42).  
The digital potentiometer easily generates a voltage divider at  
wiper to B and wiper to A, proportional to the input voltage at  
A to B. Unlike the polarity of VDD to GND, which must be  
positive, voltage across A to B, W to A, and W to B can be at  
either polarity.  
V
DD  
V
I
A
A
W
B
W
V
O
B
GND  
Figure 39. Potentiometer Mode Configuration  
Figure 42. Maximum Terminal Voltages Set by VDD and GND  
If ignoring the effect of the wiper resistance for approximation,  
connecting the A terminal to 5 V and the B terminal to ground  
produces an output voltage at the wiper to B, starting at 0 V up  
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage  
applied across Terminal A and Terminal B divided by the  
256 positions of the potentiometer divider. The general equation  
defining the output voltage at VW with respect to ground for any  
valid input voltage applied to Terminal A and Terminal B is  
POWER-UP SEQUENCE  
Because the ESD protection diodes limit the voltage compliance  
at the A, B, and W terminals (see Figure 42), it is important to  
power VDD/GND before applying voltage to the A, B, and W  
terminals; otherwise, the diode is forward-biased such that VDD  
is powered unintentionally and may affect the rest of the user’s  
circuit. The ideal power-up sequence is in the following order:  
GND, VDD, digital inputs, and then VA, VB, and VW. The relative  
order of powering VA, VB, VW, and the digital inputs is not  
important, as long as they are powered after VDD/GND.  
D
256 − D  
VW (D) =  
VA +  
VB  
(3)  
256  
256  
Operation of the digital potentiometer in the divider mode  
results in more accurate operation over temperature. Unlike in  
the rheostat mode, the output voltage is dependent mainly on  
the ratio of the internal resistors, RWA and RWB, not on the  
absolute values. Therefore, the temperature drift reduces to  
15 ppm/°C.  
LAYOUT AND POWER SUPPLY BYPASSING  
It is a good practice to employ compact, minimum lead length  
layout design. The leads to the inputs should be as direct as  
possible with a minimum conductor length. Ground paths  
should have low resistance and low inductance.  
Similarly, it is also good practice to bypass the power supplies with  
quality capacitors for optimum stability. Supply leads to the device  
should be bypassed with disc or chip ceramic capacitors of 0.01 µF  
to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors  
should also be applied at the supplies to minimize any transient  
disturbance and low frequency ripple (see Figure 43). In addition,  
note that the digital ground should be joined remotely to the  
analog ground at one point to minimize the ground bounce.  
ESD PROTECTION  
All digital inputs are protected with a series of input resistors  
and parallel Zener ESD structures, as shown in Figure 40 and  
Figure 41. This applies to the SDA, SCL, AD0, and AD1 digital  
input pins (AD5248 only).  
340Ω  
LOGIC  
GND  
Figure 40. ESD Protection of Digital Pins  
V
V
DD  
DD  
+
C3  
10µF  
C1  
0.1µF  
A, B, W  
AD5243  
GND  
GND  
Figure 41. ESD Protection of Resistor Terminals  
Figure 43. Power Supply Bypassing  
Rev. B | Page 14 of 20  
 
 
 
 
 
 
 
 
 
1...11121314151617...20

下载PDF

与AD5248BRMZ100相关器件

型号 品牌 描述 获取价格 数据表
AD5248BRMZ100-RL7 ADI Dual, 256-Position, I2C-Compatible Digital Potentiometers

获取价格
AD5248BRMZ10-RL7 ADI Dual, 256-Position, I2C-Compatible Digital Potentiometers

获取价格
AD5248BRMZ2.5 ADI Dual, 256-Position, I2C-Compatible Digital Potentiometers

获取价格
AD5248BRMZ2.5-RL7 ADI Dual, 256-Position, I2C-Compatible Digital Potentiometers

获取价格
AD5248BRMZ50 ADI Dual, 256-Position, I2C-Compatible Digital Potentiometers

获取价格
AD5248BRMZ50-RL7 ADI Dual, 256-Position, I2C-Compatible Digital Potentiometers

获取价格

与AD5248BRMZ100相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证