Datasheet > AD5246BKS100-RL7

AD5246BKS100-RL7

更新时间： 2024-02-28 19:08:32

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		光电二极管转换器电阻器
页数	文件大小	规格书
17页	1435K
描述
100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDSO6, 2 X 2.10 MM, MO-203AB, SC-70, 6 PIN

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AD5246BKS100-RL7 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	6
Reach Compliance Code：	unknown	风险等级：	5.36
Is Samacsys：	N	其他特性：	IT CAN ALSO OPERATE FROM A 5V NOMINAL SUPPLY
标称带宽：	0.04 kHz	控制接口：	2-WIRE SERIAL
转换器类型：	DIGITAL POTENTIOMETER	JESD-30 代码：	R-PDSO-G6
JESD-609代码：	e0	长度：	2 mm
湿度敏感等级：	1	功能数量：	1
位置数：	128	端子数量：	6
最高工作温度：	125 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	240	认证状态：	COMMERCIAL
电阻定律：	LINEAR	最大电阻容差：	20%
最大电阻器端电压：	3 V	最小电阻器端电压：
座面最大高度：	1.1 mm	标称供电电压：	3 V
表面贴装：	YES	标称温度系数：	45 ppm/ °C
温度等级：	AUTOMOTIVE	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
标称总电阻：	100000 Ω	宽度：	1.25 mm
Base Number Matches：	1

AD5246BKS100-RL7 数据手册

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AD5246

OPERATION

I²C COMPATIBLE 2-WIRE SERIAL BUS

The AD5246 is a 128-position, digitally controlled variable

resistor (VR) device.

The first byte of the AD5246 is a slave address byte (see Table 6

and Table 7). It has a 7-bit slave address and an R/ bit. The

PROGRAMMING THE VARIABLE RESISTOR

seven MSBs of the slave address are 0101110 followed by 0

for a write command or 1 to place the device in read mode.

Rheostat Operation

The nominal resistance of the RDAC between Terminal A

and Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.

The final two or three digits of the part number determine

the nominal resistance value, that is, 10 kΩ = 10, 50 kΩ = 50.

The nominal resistance (R_AB) of the VR has 128 contact points

accessed by the wiper terminal. The 7-bit data in the RDAC

latch is decoded to select one of the 128 possible settings.

The 2-wire I²C serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high (see Figure 27). The

following byte is the slave address byte, which consists of

the 7-bit slave address followed by an R/ bit (this bit

determines whether data will be read from or written to

the slave device).

The general equation determining the digitally programmed

output resistance between W and B is

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is termed the acknowledge bit).

At this stage, all other devices on the bus remain idle while

the selected device waits for data to be written to or read

(1)

R_WB(D) =

× R_AB+ 2× R_W

128

where:

D is the decimal equivalent of the binary code loaded in the

7-bit RDAC register.

from its serial register. If the R/ bit is high, the master

_ABis the end-to-end resistance.

_Wis the wiper resistance contributed by the on resistance

reads from the slave device. Conversely, if the R/ bit is

low, the master writes to the slave device.

of each internal switch.

2. In write mode, after acknowledgement of the slave address

byte, the next byte is the data byte. Data is transmitted over

the serial bus in sequences of nine clock pulses (eight data

bits followed by an acknowledge bit). The transitions on

the SDA line must occur during the low period of SCL and

remain stable during the high period of SCL (see Table 6).

R_S

3. In read mode, after acknowledgment of the slave address

byte, data is received over the serial bus in sequences of

nine clock pulses (a slight difference from the write mode

where eight data bits are followed by an acknowledge bit).

Similarly, the transitions on the SDA line must occur

during the low period of SCL and remain stable during

the high period of SCL (see Figure 28).

RDAC

LATCH

AND

DECODER

R_S

Figure 29. AD5246 Equivalent RDAC Circuit

4. When all data bits have been read or written, a STOP

condition is established by the master. A STOP condition

is defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master pulls the SDA line

high during the tenth clock pulse to establish a STOP

condition (see Figure 27). In read mode, the master issues

a No Acknowledge for the ninth clock pulse (that is, the

SDA line remains high). The master then brings the SDA

line low before the tenth clock pulse, which goes high to

establish a STOP condition (see Figure 28).

Note that in the zero-scale condition, there is a relatively small

finite wiper resistance. Care should be taken to limit the current

flow between W and B in this state to a maximum pulse current

of no more than 20 mA. Otherwise, degradation or possible

destruction of the internal switch contact can occur.

Typical device-to-device matching is process lot dependent and

may vary by up to 30ꢀ. Since the resistance element is proc-

essed in thin-film technology, the temperature coefficient of

R_ABis only 45 ppm/°C.

Rev. A | Page 13 of 16

1...11 12 131415 16 17

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与AD5246BKS100-RL7相关器件

型号	品牌	描述	获取价格	数据表
AD5246BKS10-R2	ADI	128-Position I2C Compatible Digital Resistor	获取价格
AD5246BKS10-R2	ROCHESTER	10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDSO6, 2 X 2.10	获取价格
AD5246BKS10-RL7	ADI	128-Position I2C Compatible Digital Resistor	获取价格
AD5246BKS50-R2	ADI	128-Position I2C Compatible Digital Resistor	获取价格
AD5246BKS50-RL7	ADI	128-Position I2C Compatible Digital Resistor	获取价格
AD5246BKS50-RL7	ROCHESTER	50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDSO6, 2 X 2.10	获取价格

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