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AD5246BKS100-RL7 PDF预览

AD5246BKS100-RL7

更新时间: 2024-02-29 04:50:08
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管转换器电阻器
页数 文件大小 规格书
17页 1435K
描述
100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDSO6, 2 X 2.10 MM, MO-203AB, SC-70, 6 PIN

AD5246BKS100-RL7 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:6
Reach Compliance Code:unknown风险等级:5.36
Is Samacsys:N其他特性:IT CAN ALSO OPERATE FROM A 5V NOMINAL SUPPLY
标称带宽:0.04 kHz控制接口:2-WIRE SERIAL
转换器类型:DIGITAL POTENTIOMETERJESD-30 代码:R-PDSO-G6
JESD-609代码:e0长度:2 mm
湿度敏感等级:1功能数量:1
位置数:128端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240认证状态:COMMERCIAL
电阻定律:LINEAR最大电阻容差:20%
最大电阻器端电压:3 V最小电阻器端电压:
座面最大高度:1.1 mm标称供电电压:3 V
表面贴装:YES标称温度系数:45 ppm/ °C
温度等级:AUTOMOTIVE端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
标称总电阻:100000 Ω宽度:1.25 mm
Base Number Matches:1

AD5246BKS100-RL7 数据手册

 浏览型号AD5246BKS100-RL7的Datasheet PDF文件第11页浏览型号AD5246BKS100-RL7的Datasheet PDF文件第12页浏览型号AD5246BKS100-RL7的Datasheet PDF文件第13页浏览型号AD5246BKS100-RL7的Datasheet PDF文件第14页浏览型号AD5246BKS100-RL7的Datasheet PDF文件第16页浏览型号AD5246BKS100-RL7的Datasheet PDF文件第17页 
AD5246  
V
DD  
A repeated write function gives the user flexibility to update the  
RDAC output a number of times after addressing the part only  
once. For example, after the RDAC has acknowledged its slave  
address in write mode, the RDAC output updates on each succes-  
sive byte. If different instructions are needed, the write/read mode  
has to start again with a new slave address and data byte.  
B
W
Similarly, a repeated read function of the RDAC is also allowed.  
GND  
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE  
Figure 32. Maximum Terminal Voltages Set by VDD and GND  
While most legacy systems may be operated at one voltage,  
a new component may be optimized at another. When two  
systems operate the same signal at two different voltages, proper  
level shifting is needed. For instance, one can use a 1.8 V  
E2PROM to interface with a 5 V digital potentiometer. A level  
shifting scheme is needed to enable a bidirectional communi-  
cation so that the setting of the digital potentiometer can be  
stored to and retrieved from the E2PROM. Figure 30 shows  
one of the implementations. M1 and M2 can be any N channel  
signal FETs, or if VDD falls below 2.5 V, M1 and M2 can be low  
threshold FETs such as the FDV301N.  
MAXIMUM OPERATING CURRENT  
At low code values, the user should be aware that due to low  
resistance values, the current through the RDAC may exceed  
the 5 mA limit. In Figure 33, a 5 V supply is placed on the  
wiper, and the current through Terminal W and Terminal B is  
plotted with respect to code. A line is also drawn denoting the  
5 mA current limit. Note that at low code values (particularly  
for the 5 kꢁ and 10 kꢁ options), the current level increases  
significantly. Care should be taken to limit the current flow  
between W and B in this state to a maximum continuous  
current of 5 mA and a maximum pulse current of no more than  
20 mA. Otherwise, degradation or possible destruction of the  
internal switch contacts can occur.  
V
= 1.8V  
V
= 5V  
DD1  
DD2  
R
R
R
R
P
P
P
P
G
S
D
SDA2  
SDA1  
SCL1  
100  
G
M1  
S
D
SCL2  
M2  
1.8V  
5V  
10  
5mA CURRENT LIMIT  
E2PROM  
AD5246  
R
= 5kΩ  
AB  
1
Figure 30. Level Shifting for Operation at Different Potentials  
R
= 10kΩ  
AB  
R
= 50kΩ  
AB  
0.1  
ESD PROTECTION  
R
= 100k  
96  
Ω
All digital inputs are protected with a series input resistor  
and parallel Zener ESD structures, as shown in Figure 31.  
This applies to the digital input pins SDA and SCL.  
AB  
0.01  
64  
80  
112  
128  
0
16  
32  
48  
CODE (Decimal)  
Figure 33. Maximum Operating Current  
340Ω  
LOGIC  
POWER-UP SEQUENCE  
GND  
Since the ESD protection diodes limit the voltage compliance  
at Terminal B and Terminal W (see Figure 32), it is important  
to power VDD/GND before applying any voltage to Terminal B  
and Terminal W% otherwise, the diode is forward biased such  
that VDD is powered unintentionally and may affect the rest of  
the users circuit. The ideal power-up sequence is in the follow-  
ing order: GND, VDD, digital inputs, and then VB/VW. The  
relative order of powering VB and VW and the digital inputs  
is not important, providing they are powered after VDD/GND.  
Figure 31. ESD Protection of Digital Pins  
TERMINAL VOLTAGE OPERATING RANGE  
The AD5246 VDD and GND power supply defines the boundary  
conditions for proper 3-terminal digital potentiometer  
operation. Supply signals present on Terminal B and  
Terminal W that exceed VDD or GND are clamped by  
the internal forward biased diodes (see Figure 32).  
Rev. A | Page 14 of 16  
 

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