Datasheet > AD5206_15

AD5206_15

更新时间： 2022-02-26 13:53:33

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	371K
描述
4-/6-Channel Digital Potentiometers

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中文翻译

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数据手册

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AD5206_15 数据手册

AD5204/AD5206

24 B4

23 W4

22 A4

21 B2

20 W2

19 A2

GND

AD5206

TOP VIEW

(Not to Scale)

SDI

17 W1

16 B1

15 A3

14 W3

13 B3

CLK

B5 10

W5 11

A5 12

NC = NO CONNECT

Figure 8. AD5206 SOIC/TSSOP/PDIP Pin Configuration

Table 5. AD5206 Pin Function Descriptions

Pin No.

Name

Description

ꢀ

GND

Terminal A RDAC 6.

Wiper RDAC 6. Address = 101₂.

Terminal B RDAC 6.

Ground.

Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the

address bits, and then it is loaded into the target RDAC latch.

V_DD

SDI

CLK

V_SS

Bꢀ

Wꢀ

Aꢀ

Positive Power Supply. This pin is specified for operation at both 3 V and ꢀ V. It is the sum of |V_DD| + |V_SS| < ꢀ.ꢀ V.

Serial Data Input. Data is input MSB first.

Serial Clock Input. This pin is positive edge triggered.

Negative Power Supply. This pin is specified for operation at both 0 V and −2.7 V. It is the sum of |V_DD| + |V_SS| < ꢀ.ꢀ V.

Terminal B RDAC ꢀ.

Wiper RDAC ꢀ. Address = 100₂.

Terminal A RDAC ꢀ.

Terminal B RDAC 3.

Wiper RDAC 3. Address = 010₂.

Terminal A RDAC 3.

Terminal B RDAC 1.

Wiper RDAC 1. Address = 000₂.

Terminal A RDAC 1.

Terminal A RDAC 2.

Wiper RDAC 2. Address = 001₂.

Terminal B RDAC 2.

Terminal A RDAC 4.

Wiper RDAC 4. Address = 011₂.

Terminal B RDAC 4.

1ꢀ

Rev. C | Page 9 of 20

1...6 7 8910 11 12...20

中文翻译

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