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AD5172BRMZ50 PDF预览

AD5172BRMZ50

更新时间: 2024-02-20 11:25:41
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管转换器电阻器
页数 文件大小 规格书
28页 826K
描述
256-Position, One-Time Programmable, Dual Channel, I<sup>2</sup>C Digital Potentiometer

AD5172BRMZ50 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP10,.19,20针数:10
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.25
其他特性:IT CAN ALSO OPERATE FROM 5 V NOMINAL SUPPLY标称带宽:0.1 kHz
控制接口:2-WIRE SERIAL转换器类型:DIGITAL POTENTIOMETER
JESD-30 代码:S-PDSO-G10JESD-609代码:e3
长度:3 mm湿度敏感等级:1
功能数量:2位置数:256
端子数量:10最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP10,.19,20
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified电阻定律:LINEAR
最大电阻容差:20%最大电阻器端电压:5.5 V
最小电阻器端电压:座面最大高度:1.1 mm
子类别:Digital Potentiometers标称供电电压:3 V
表面贴装:YES标称温度系数:35 ppm/ °C
温度等级:AUTOMOTIVE端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
标称总电阻:50000 Ω宽度:3 mm
Base Number Matches:1

AD5172BRMZ50 数据手册

 浏览型号AD5172BRMZ50的Datasheet PDF文件第6页浏览型号AD5172BRMZ50的Datasheet PDF文件第7页浏览型号AD5172BRMZ50的Datasheet PDF文件第8页浏览型号AD5172BRMZ50的Datasheet PDF文件第10页浏览型号AD5172BRMZ50的Datasheet PDF文件第11页浏览型号AD5172BRMZ50的Datasheet PDF文件第12页 
Data Sheet  
AD5172/AD5173  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
1
2
3
4
5
10 W1  
B1  
AD0  
W2  
1
2
3
4
5
10 W1  
B1  
A1  
9
8
7
6
B2  
9
8
7
6
B2  
AD5173  
TOP VIEW  
(Not to Scale)  
AD5172  
TOP VIEW  
(Not to Scale)  
AD1  
SDA  
SCL  
W2  
A2  
GND  
GND  
SDA  
SCL  
V
V
DD  
DD  
Figure 4. AD5172 Pin Configuration  
Figure 5. AD5173 Pin Configuration  
Table 5. AD5172 Pin Function Descriptions  
Table 6. AD5173 Pin Function Descriptions  
Pin  
Pin  
No. Mnemonic Description  
No. Mnemonic Description  
1
2
3
4
5
B1  
A1  
W2  
GND  
VDD  
B1 Terminal. GND ≤ VB1 ≤ VDD.  
A1 Terminal. GND ≤ VA1 ≤ VDD.  
W2 Terminal. GND ≤ VW2 ≤ VDD.  
Digital Ground.  
Positive Power Supply. Specified for  
operation from 2.7 V to 5.5 V. For OTP  
programming, VDD needs to be a minimum  
of 5.6 V but no more than 5.8 V and to be  
capable of driving 100 mA.  
Serial Clock Input. Positive-edge triggered.  
Requires a pull-up resistor. If this pin is driven  
directly from a logic controller without a  
pull-up resistor, ensure that the VIH minimum  
is 0.7 V × VDD.  
Serial Data Input/Output. Requires a pull-up  
resistor. If this pin is driven directly from a  
logic controller without a pull-up resistor,  
ensure that the VIH minimum is 0.7 V × VDD.  
1
2
B1  
AD0  
B1 Terminal. GND ≤ VB1 ≤ VDD.  
Programmable Address Bit 0 for Multiple  
Package Decoding.  
W2 Terminal. GND ≤ VW2 ≤ VDD.  
Digital Ground.  
Positive Power Supply. Specified for  
operation from 2.7 V to 5.5 V. For OTP  
programming, VDD needs to be a minimum  
of 5.6 V but no more than 5.8 V and to be  
capable of driving 100 mA.  
Serial Clock Input. Positive-edge triggered.  
Requires a pull-up resistor. If this pin is driven  
directly from a logic controller without a  
pull-up resistor, ensure that the VIH minimum  
is 0.7 V × VDD.  
Serial Data Input/Output. Requires a pull-up  
resistor. If this pin is driven directly from a  
logic controller without a pull-up resistor,  
ensure that the VIH minimum is 0.7 V × VDD.  
Programmable Address Bit 1 for Multiple  
Package Decoding.  
B2 Terminal. GND ≤ VB2 ≤ VDD.  
W1 Terminal. GND ≤ VW1 ≤ VDD.  
3
4
5
W2  
GND  
VDD  
6
7
SCL  
6
SCL  
SDA  
7
8
SDA  
AD1  
8
9
10  
A2  
B2  
W1  
A2 Terminal. GND ≤ VA2 ≤ VDD.  
B2 Terminal. GND ≤ VB2 ≤ VDD.  
W1 Terminal. GND ≤ VW1 ≤ VDD.  
9
10  
B2  
W1  
Rev. I | Page 9 of 28  
 

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