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AD5172BRM50-R2 PDF预览

AD5172BRM50-R2

更新时间: 2024-01-17 12:42:20
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管转换器电阻器
页数 文件大小 规格书
19页 315K
描述
IC DUAL 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.90 MM, MO-187BA, MSOP-10, Digital Potentiometer

AD5172BRM50-R2 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:3 X 4.90 MM, MO-187BA, MSOP-10针数:10
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.28
其他特性:IT CAN ALSO OPERATE FROM 5 V NOMINAL SUPPLY标称带宽:0.1 kHz
控制接口:2-WIRE SERIAL转换器类型:DIGITAL POTENTIOMETER
JESD-30 代码:S-PDSO-G10JESD-609代码:e0
长度:3 mm功能数量:2
位置数:256端子数量:10
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP10,.19,20封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/5 V认证状态:Not Qualified
电阻定律:LINEAR最大电阻容差:20%
最大电阻器端电压:5.5 V最小电阻器端电压:
座面最大高度:1.1 mm子类别:Digital Potentiometers
标称供电电压:3 V表面贴装:YES
技术:CMOS标称温度系数:35 ppm/ °C
温度等级:AUTOMOTIVE端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
标称总电阻:50000 Ω宽度:3 mm
Base Number Matches:1

AD5172BRM50-R2 数据手册

 浏览型号AD5172BRM50-R2的Datasheet PDF文件第7页浏览型号AD5172BRM50-R2的Datasheet PDF文件第8页浏览型号AD5172BRM50-R2的Datasheet PDF文件第9页浏览型号AD5172BRM50-R2的Datasheet PDF文件第11页浏览型号AD5172BRM50-R2的Datasheet PDF文件第12页浏览型号AD5172BRM50-R2的Datasheet PDF文件第13页 
AD5172/AD5173  
Preliminary Technical Data  
Table 8. RWB vs. Codes; RAB = 10 kand  
the A Terminal Is Opened  
potentiometer mode. The most common configuration is the  
voltage divider operation (Figure 29).  
D (Dec)  
RWB (Ω)  
9,9ꢁ1  
5,0ꢁ0  
99  
Output State  
255  
128  
1
Full Scale (RAB – 1 LSB + RW)  
Midscale  
1 LSB  
V
I
A
B
W
V
O
0
ꢁ0  
Zero Scale (Wiper Contact Resistance)  
Since a finite wiper resistance of 60 Ω is present in the zero-  
scale condition, care should be taken to limit the current flow  
between W and B in this state to a maximum pulse current of  
no more than 20 mA. Otherwise, degradation or possible  
destruction of the internal switch contact can occur.  
Figure 29. Potentiometer Mode Configuration  
The transfer function can be found as  
D
256  
RAB + 2RW  
RAB + RW  
Similar to the mechanical potentiometer, the resistance of the  
RDAC between the wiper W and terminal A also produces a  
complementary resistance RWA (AD5172 only). When these  
terminals are used, the B terminal can be opened or shorted to  
W. Setting the resistance value for RWA starts at a maximum  
value of resistance and decreases as the data loaded in the latch  
increases in value. The general equation for this operation is  
VW (D) =  
VA  
(AD5172 only) (3)  
If we ignore the effect of the wiper resistance, the transfer  
function is simply  
D
256  
256 D  
VW (D) =  
VA  
(AD5172 only)  
(4)  
RWA (D) =  
RAB + RW (AD5172 only) (2)  
256  
Table 9. RWA vs. Codes; RAB =10 kand  
Unlike in rheostat mode operation where the absolute tolerance  
is high, potentiometer mode operation yields an almost ratio-  
metric function of D/256 with a relatively small error  
contributed by the RW terms, and therefore the tolerance effect is  
almost cancelled. Although the thin film step resistor RS and CMOS  
switches resistance RW have very different temperature coefficients,  
the ratio-metric adjustment also reduces the overall temperature  
coefficient effect to 5 ppm/oC, except at low value codes where RW  
dominates.  
B Terminal Is Opened  
D (Dec)  
RWA (Ω)  
Output State  
Full Scale  
Midscale  
1 LSB  
255  
128  
1
99  
5,0ꢁ0  
9,9ꢁ1  
10,0ꢁ0  
0
Zero Scale  
The typical distribution of the resistance tolerance from device  
to device is process lot dependent, and it is possible to have  
30% tolerance.  
Potentiometer mode operations include others such as op amp  
input, feedback resistor networks, and other voltage scaling  
applications. A, W, and B terminals can in fact be input or output  
terminals provided that |VAB|, |VWA|, and |VWB| do not exceed  
A
VDD to GND.  
SD BIT  
RS  
ESD PROTECTION  
D7  
D6  
Digital inputs SDA and SCL are protected with a series input  
resistor and parallel Zener ESD structures (Figure30).  
RS  
D5  
D4  
D3  
D2  
RS  
D1  
340  
D0  
W
LOGIC  
RDAC  
LATCH  
RS  
Figure30. ESD Protection of Digital Pins  
AND  
B
DECODER  
TERMINAL VOLTAGE OPERATING RANGE  
Figure 28. Equivalent RDAC Circuit (A terminal for AD5172 only)  
There are also ESD protection diodes between VDD and the  
RDAC terminals. The VDD of AD5172/73 therefore defines their  
voltage boundary conditions, see Figure31. Supply signals  
Potentiometer Mode Operation (AD5172 only)  
If all three terminals are used, the operation is called the  
Rev. PrF 8/14/03 | Page 10 of 19  

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