Datasheet > AD5170BRM2.5-RL7

AD5170BRM2.5-RL7

更新时间： 2024-01-25 12:13:08

品牌	Logo	应用领域
亚德诺 - ADI		数字电位计
页数	文件大小	规格书
24页	1077K
描述
256-Position Two-Time Programmable I2C Digital Potentiometer

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技术参数
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AD5170BRM2.5-RL7 技术参数

Source Url Status Check Date：	2013-05-01 14:56:10.393	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	3 X 4.90 MM, MO-187BA, MSOP-10
针数：	10	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.68	其他特性：	IT CAN ALSO OPERATE FROM A 5V NOMINAL SUPPLY
标称带宽：	4.8 kHz	控制接口：	2-WIRE SERIAL
转换器类型：	DIGITAL POTENTIOMETER	JESD-30 代码：	S-PDSO-G10
JESD-609代码：	e0	长度：	3 mm
湿度敏感等级：	1	功能数量：	1
位置数：	256	端子数量：	10
最高工作温度：	125 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP10,.19,20	封装形状：	SQUARE
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	240
电源：	3/5 V	认证状态：	Not Qualified
电阻定律：	LINEAR	最大电阻容差：	55%
最大电阻器端电压：	5.5 V	最小电阻器端电压：
座面最大高度：	1.1 mm	子类别：	Digital Potentiometers
标称供电电压：	3 V	表面贴装：	YES
标称温度系数：	35 ppm/ °C	温度等级：	AUTOMOTIVE
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	标称总电阻：	2500 Ω
宽度：	3 mm	Base Number Matches：	1

AD5170BRM2.5-RL7 数据手册

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AD5170

I²C COMPATIBLE 2-WIRE SERIAL BUS

The 2-wire I²C serial bus protocol operates as follows:

The fifth MSB, OW, is an overwrite bit. When raised to a

logic high, OW allows the RDAC setting to be changed

even after the internal fuses have been blown. However,

once OW is returned to a logic zero, the position of the

RDAC returns to the setting prior to overwrite. Because

OW is not static, if the device is powered off and on, the

RDAC presets to midscale or to the setting at which the

fuses were blown, depending on whether the fuses have

been permanently set.

1. The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high (see Figure 45). The

following byte is the slave address byte, which consists of

the slave address followed by an R/ bit (this bit deter-

mines whether data is read from, or written to, the slave

device). AD0 and AD1 are configurable address bits which

allow up to four devices on one bus (see Table 7).

The remainder of the bits in the instruction byte are Don’t

Care bits (see Figure 45).

The slave address corresponding to the transmitted address

bits responds by pulling the SDA line low during the ninth

clock pulse (this is termed the Acknowledge bit). At this

stage, all other devices on the bus remain idle while the

selected device waits for data to be written to, or read from,

After acknowledging the instruction byte, the last byte in

write mode is the data byte. Data is transmitted over the

serial bus in sequences of nine clock pulses (eight data bits

followed by an Acknowledge bit). The transitions on the

SDA line must occur during the low period of SCL and

remain stable during the high period of SCL (see

Figure 44).

its serial register. If the R/ bit is high, the master will read

from the slave device. If the R/ bit is low, the master will

write to the slave device.

2. In the write mode, the second byte is the instruction byte.

The first bit (MSB), 2T, of the instruction byte is the

second trim enable bit. A logic low selects the first array of

fuses, and a logic high selects the second array. This means

that after blowing the fuses with trim#1, the user still has

another chance to blow them again with trim#2. Note that

using trim#2 before trim#1 effectively disables trim#1 and,

in turn, only allows one-time programming.

3. In the read mode, the data byte follows immediately after

the acknowledgment of the slave address byte. Data is

transmitted over the serial bus in sequences of nine clock

pulses (a slight difference from the write mode, with eight

data bits followed by an Acknowledge bit). Similarly, the

transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of

SCL (see Figure 46).

The second MSB, SD, is a shutdown bit. A logic high causes

an open circuit at Terminal A while shorting the wiper to

Terminal B. This operation yields almost 0 Ω in rheostat

mode or 0 V in potentiometer mode. It is important to

note that the shutdown operation does not disturb the

contents of the register. When brought out of shutdown,

the previous setting is applied to the RDAC. Also, during

shutdown, new settings can be programmed. When the

part is returned from shutdown, the corresponding VR

setting is applied to the RDAC.

Following the data byte, the validation byte contains two

validation bits, E0 and E1. These bits signify the status of

the one-time programming (see Figure 46).

4. After all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master pulls the SDA line

high during the 10^thclock pulse to establish a STOP

condition (see Figure 45). In read mode, the master issues a

No Acknowledge for the 9^thclock pulse (i.e., the SDA line

remains high). The master then brings the SDA line low

before the 10^thclock pulse, which goes high to establish a

STOP condition (see Figure 46).

The third MSB, T, is the OTP (one-time programmable)

programming bit. A logic high blows the poly fuses and

programs the resistor setting permanently. For example, if

the user wanted to blow the first array of fuses, the

instruction byte would be 00100XXX. To blow the second

array of fuses, the instruction byte would be 10100XXX. A

logic low of the T bit simply allows the device to act as a

typical volatile digital potentiometer.

A repeated write function gives the user flexibility to update the

RDAC output a number of times after addressing and instructing

the part only once. For example, after the RDAC has acknowledged

its slave address and instruction bytes in the write mode, the

RDAC output updates on each successive byte. If different

instructions are needed, the write/read mode has to start again

with a new slave address, instruction, and data byte. Similarly, a

repeated read function of the RDAC is also allowed.

The fourth MSB must always be at Logic 0.

Rev. A | Page 2± of 24

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AD5171BRJ50-R2	ADI	64-Position OTP Digital Potentiometer	获取价格
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