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AD5044BRUZ PDF预览

AD5044BRUZ

更新时间： 2024-02-17 20:54:19
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 1271K
描述
Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP

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中文翻译

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AD5044BRUZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.83
Samacsys Description：14BIT Digital-to-Analog Converters (DAC)最大模拟输出电压：5.5 V
最小模拟输出电压：转换器类型：D/A CONVERTER
输入位码：BINARY输入格式：SERIAL
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：5 mm最大线性误差 (EL)：0.0061%
湿度敏感等级：1位数：14
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
座面最大高度：1.2 mm标称安定时间 (tstl)：10.7 µs
子类别：Other Converters最大压摆率：6 mA
标称供电电压：5 V表面贴装：YES
温度等级：AUTOMOTIVE端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mm

AD5044BRUZ 数据手册

 浏览型号AD5044BRUZ的Datasheet PDF文件第5页浏览型号AD5044BRUZ的Datasheet PDF文件第6页浏览型号AD5044BRUZ的Datasheet PDF文件第7页浏览型号AD5044BRUZ的Datasheet PDF文件第9页浏览型号AD5044BRUZ的Datasheet PDF文件第10页浏览型号AD5044BRUZ的Datasheet PDF文件第11页 
AD5024/AD5044/AD5064  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
LDAC  
SYNC  
1
2
3
4
5
6
7
8
16 SCLK  
15 DIN  
V
14  
13  
12  
11  
10  
9
GND  
DD  
AD5024/  
AD5044/  
AD5064  
V
B
D
OUT  
V
V
V
B
A
A
C
REF  
REF  
V
OUT  
TOP VIEW  
(Not to Scale)  
V
D
REF  
OUT  
OUT  
V
CLR  
V
C
POR  
REF  
Figure 3. 16-Lead TSSOP (RU-16) Pin Configuration  
Table 6. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
LDAC  
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This  
allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.  
2
SYNC  
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes  
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on  
the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge  
of SYNC acts as an interrupt and the write sequence is ignored by the device.  
3
VDD  
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled  
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.  
4
5
6
ꢀ
8
VREF  
VREF  
VOUT  
VOUT  
B
A
A
C
DAC B Reference Input. This is the reference voltage input pin for DAC B.  
DAC A Reference Input. This is the reference voltage input pin for DAC A.  
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.  
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.  
Power-On Reset. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up the  
part to midscale.  
POR  
9
VREF  
C
DAC C Reference Input .This is the reference voltage input pin for DAC C.  
10  
CLR  
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are  
ignored. When CLR is activated, the input register and the DAC register are updated with the data  
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.  
11  
12  
13  
14  
15  
VREF  
VOUT  
VOUT  
GND  
DIN  
D
D
B
DAC D Reference Input .This is the reference voltage input pin for DAC D.  
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.  
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.  
Ground Reference Point for All Circuitry on the Part.  
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling  
edge of the serial clock input.  
16  
SCLK  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.  
Data can be transferred at rates of up to 50 MHz.  
Rev. 0 | Page 8 of 28  
 
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中文翻译

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AD5044BRUZ 替代型号

型号 品牌 替代类型 描述 数据表
AD5064BRUZ-REEL7 ADI

类似代替

 Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
AD5064BRUZ ADI

类似代替

 Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
AD5044BRUZ-REEL7 ADI

类似代替

 Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP

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