Datasheet > AD484M1644VTA-8LI

AD484M1644VTA-8LI

更新时间： 2022-11-29 04:15:25

品牌	Logo	应用领域
其他 - ETC		半导体动态存储器
页数	文件大小	规格书
20页	86K
描述
Ascend Semiconductor Corporation(64Mb SDRAM)

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AD484M1644VTA-8LI 数据手册

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Ascend Semiconductor Corporation

64Mb SDRAM

Pin Descriptions ( Simplified )

CLK

/CS

Name

System Clock

Chip select

Pin Function

Master Clock Input(Active on the Positive rising edge)

Selects chip when active

Activates the CLK when“H” and deactivates when“L”.

CKE should be enabled at least one cycle prior to new

command. Disable input buffers for power down in standby.

CKE

Clock Enable

Row address (A0 to A11) is determined by A0 to A11 level

at the bank active command cycle CLK rising edge.

CA(CA0 to CA7) is determined by A0 to A7 level at the

read or write command cycle CLK rising edge.

A0 ~ A11

Address

And this column address becomes burst access start

address. A10 defines the pre-charge mode. When A10 = High

at the pre-charge command cycle, all banks are pre-charged.

But when A10 = Low at the pre-charge command cycle,

only the bank that is selected by BA0/BA1 is pre-charged.

BA0, BA1

/RAS

Bank Address

Row address strobe

Column address strobe

Write Enable

Selects which bank is to be active.

Latches Row Addresses on the positive rising edge of the

CLK with /RAS “L” . Enables row access & pre-charge.

Latches Column Addresses on the positive rising edge of the

CLK with /CAS low. Enables column access.

/CAS

Latches Column Addresses on the positive rising edge of the

CLK with /CAS low. Enables column access.

/WE

LDQM/ UDQM

DQ0 ~ 15

Data input/output Mask

Data input/output

DQM controls I/O buffers.

DQ pins have the same function as I/O pins on a conventional

DRAM.

VDD/VSS

Power supply/Ground

VDD and VSS are power supply pins for internal circuits.

VDDQ and VSSQ are power supply pins for the output buffers.

VDDQ/VSSQ

This pin is recommended to be left No Connection on the

device.

No connection

Preliminary

1 2 3 456 7 8...20

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