Datasheet > AD4630-16

AD4630-16

更新时间： 2023-12-20 18:44:57

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
51页	2023K
描述
16位、2 MSPS、双通道SAR ADC

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AD4630-16 数据手册

Data Sheet

AD4630-16/AD4632-16

SPECIFICATIONS

Figure 4. Register Configuration Mode Read Timing

Figure 5. Register Configuration Mode Command Timing

Table 4. SPI-Compatible Mode Timing

Parameter

Symbol

Min

Typ

Max

Unit

SCK Period

t_SCK

VIO > 1.71 V

9.8

VIO > 1.14 V

12.3

SCK Low Time

t_SCKL

VIO > 1.71 V

4.2

5.2

VIO > 1.14 V

SCK High Time

t_SCKH

VIO > 1.71 V

4.2

5.2

1.4

VIO > 1.14 V

SCK Falling Edge to Data Remains Valid

SCK Falling Edge to Data Valid Delay

VIO > 1.71 V

t_HSDO

t_DSDO

5.6

8.1

VIO > 1.14 V

CS Falling Edge to SDO Valid

VIO > 1.71 V

t_CSEN

6.8

9.3

VIO > 1.14 V

CS Falling Edge to First SCK Rising Edge

VIO > 1.71 V

t_CSSCK

9.8

VIO > 1.14 V

12.3

4.2

Last SCK Edge to CS Rising Edge

CS Rising Edge to SDO High Impedance

CS Falling Edge to BUSY Rising Edge

t_SCKCS

t_CSDIS

t_CSBUSY

Figure 6. SPI Clocking Mode 1-Lane Single Data-Rate (SDR) Timing

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Rev. A | 8 of 51

1...5 6 789 10 11...51

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