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AD1974_13

更新时间: 2024-11-26 01:18:11
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亚德诺 - ADI /
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24页 392K
描述
4 ADC with PLL

AD1974_13 数据手册

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4 ADC with PLL,  
192 kHz, 24-Bit ADC  
AD1974  
Data Sheet  
FEATURES  
GENERAL DESCRIPTION  
Phase-locked loop generated or direct master clock  
Low EMI design  
107 dB dynamic range and SNR  
−94 dB THD + N  
Single 3.3 V supply  
Tolerance for 5 V logic inputs  
The AD1974 is a high performance, single-chip ADC that pro-  
vides four analog-to-digital converters (ADCs) with differential  
inputs using the Analog Devices, Inc. patented multibit sigma-  
delta (Σ-Δ) architecture. An SPI port is included, allowing a  
microcontroller to enable mutes and adjust many other  
parameters. The AD1974 operates from 3.3 V digital and analog  
supplies. The AD1974 is available in a single-ended output  
48-lead L QF P.  
Supports 24 bits and 8 kHz to 192 kHz sample rates  
Differential ADC input  
SPI®-controllable for flexibility  
Software-controllable clickless mute  
Software power-down  
Right justified, left justified, I2S, and TDM modes  
Master and slave modes up to 16-channel input/output  
Available in a 48-lead LQFP  
The AD1974 is designed for low EMI. This consideration is  
apparent in both the system and circuit design architectures.  
By using the on-board phase-locked loop (PLL) to derive the  
master clock from the LR clock or from an external crystal,  
the AD1974 eliminates the need for a separate high frequency  
master clock and can also be used with a suppressed bit clock.  
The ADCs are designed using the latest continuous time archi-  
tectures from Analog Devices to further minimize EMI. By  
using 3.3 V supplies, power consumption is minimized, further  
reducing emissions.  
Qualified for automotive applications  
APPLICATIONS  
Automotive audio systems  
Home Theater Systems  
Set-top boxes  
Digital audio effects processors  
FUNCTIONAL BLOCK DIAGRAM  
DIGITAL AUDIO  
INPUT/OUTPUT  
AD1974  
SERIAL DATA PORT  
SDATA  
OUT  
ADC  
QUAD  
DEC  
FILTER  
ADC  
ADC  
ADC  
ANALOG  
AUDIO  
INPUTS  
CLOCKS  
48kHz/  
96kHz/192kHz  
TIMING MANAGEMENT  
AND CONTROL  
(CLOCK AND PLL)  
CONTROL PORT  
SPI  
PRECISION  
VOLTAGE  
REFERENCE  
12.48MHz  
CONTROL DATA  
INPUT/OUTPUT  
Figure 1.  
Rev. D  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 

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