Datasheet > 消费电路 > 其他商用集成电路> AD1895YRSRL

AD1895YRSRL

更新时间： 2024-02-04 09:53:11

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
24页	814K
描述
192 kHz Stereo Asynchronous Sample Rate Converter

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD1895YRSRL 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	PLASTIC, SSOP-28	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.64
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e0	长度：	10.2 mm
湿度敏感等级：	NOT SPECIFIED	功能数量：	1
端子数量：	28	最高工作温度：	105 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	COMMERCIAL	座面最大高度：	2 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	5.3 mm
Base Number Matches：	1

AD1895YRSRL 数据手册

AD1895

–10

–20

–30

–40

SLOW MODE

–50

FAST MODE

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–180

–190

–200

–210

–220

0.01

0.1

100

1e3

1e4

1e5

FREQUENCY – Hz

Figure 8. Frequency Response of the Digital Servo Loop. f_{S_IN}is the X-Axis, f_{S_OUT}= 192 kHz, Master Clock

Frequency Is 30 MHz

The digital servo loop is essentially a ramp filter that provides

the initial pointer to the address in RAM and ROM for the start

of the FIR convolution. The RAM pointer is the integer output

of the ramp filter while the ROM is the fractional part. The

digital servo loop must be able to provide excellent rejection of

jitter on the f_{S_IN}and f_{S_OUT}clocks as well as measure the arrival

of the f_{S_OUT}clock within 4.97 ps. The digital servo loop will

also divide the fractional part of the ramp output by the ratio of

f_{S_IN}/f_{S_OUT}for the case when f_{S_IN}> f_{S_OUT}, to dynamically alter

the ROM coefficients.

The FIR filter is a 64-tap filter in the case of f_{S_OUT}≥ f_{S_IN}and is

(f_{S_IN}/f_{S_OUT}) × 64 taps for the case when f_{S_IN}> f_{S_OUT}. The FIR

filter performs its convolution by loading in the starting address

of the RAM address pointer and the ROM address pointer

from the digital servo loop at the start of the f_{S_OUT}period.

The FIR filter then steps through the RAM by decrementing its

address by 1 for each tap, and the ROM pointer increments its

address by the (f_{S_OUT}/f_{S_IN}) × 2²⁰ratio for f_{S_IN}> f_{S_OUT}or 2²⁰

for f_{S_OUT}≥ f_{S_IN}. Once the ROM address rolls over, the con-

volution is completed. The convolution is performed for both

the left and right channels, and the multiply accumulate circuit

used for the convolution is shared between the channels.

The digital servo loop is implemented with a multirate filter. To

settle the digital servo loop filter quicker upon start-up or a change

in the sample rate, a “fast mode” was added to the filter. When

the digital servo loop starts up or the sample rate is changed, the

digital servo loop kicks into “fast mode” to adjust and settle

on the new sample rate. Upon sensing the digital servo loop

settling down to some reasonable value, the digital servo loop

will kick into “normal” or “slow mode.” During “fast mode”

the MUTE_OUT signal of the sample rate converter is asserted

to let the user know that they should mute the sample rate

converter to avoid any clicks or pops. The frequency response of

the digital servo loop for “fast mode” and “slow mode” are

shown in Figure 8.

The f_{S_IN}/f_{S_OUT}sample rate ratio circuit is used to dynamically

alter the coefficients in the ROM for the case when f_{S_IN}

_{S_OUT}. The ratio is calculated by comparing the output of an

f_{S_OUT}counter to the output of an f_{S_IN}counter. If f_{S_OUT}

_{S_IN}, the ratio is held at one. If f_{S_IN}> f_{S_OUT}, the sample rate

ratio is updated if it is different by more than two f_{S_OUT}periods

from the previous f_{S_OUT}to f_{S_IN}comparison. This is done to

provide some hysteresis to prevent the filter length from oscillat-

ing and causing distortion.

REV. A

–18–

1...15 16 171819 20 21...24

下载PDF

与AD1895YRSRL相关器件

型号	品牌	描述	获取价格	数据表
AD1896	ADI	192 kHz Stereo Asynchronous Sample Rate Converter	获取价格
AD1896AYRS	ADI	192 kHz Stereo Asynchronous Sample Rate Converter	获取价格
AD1896AYRSRL	ADI	192 kHz Stereo Asynchronous Sample Rate Converter	获取价格
AD1896AYRSZ	ADI	192 kHz Stereo Asynchronous Sample Rate Converter	获取价格
AD1896AYRSZRL	ADI	暂无描述	获取价格
AD1896YRS	ADI	192 kHz Stereo Asynchronous Sample Rate Converter	获取价格

与AD1895YRSRL相关文章

SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
2024-05-23

5
AT89C51单片机资料手册详细解析及应用示例
2024-05-23

8
CP2102资料手册解读：CP2102引脚说明、关键参数分析
2024-05-23

4
资料手册解读：UC3842参数和管脚说明
2024-05-22

5

产品中心

服务支持

精选活动

关于我们

帮助中心

AD1895YRSRL

AD1895YRSRL 技术参数

AD1895YRSRL 数据手册

与AD1895YRSRL相关器件

与AD1895YRSRL相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD1895YRSRL

AD1895YRSRL 技术参数

AD1895YRSRL 数据手册

与AD1895YRSRL相关器件

与AD1895YRSRL相关文章

您还可以找

您在本页遇到什么问题？