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ACT4468D PDF预览

ACT4468D

更新时间: 2024-01-13 09:05:20
品牌 Logo 应用领域
艾法斯 - AEROFLEX 驱动器
页数 文件大小 规格书
6页 84K
描述
ACT4468D Dual Transceivers for MIL-STD-1553

ACT4468D 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:DIP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.51
Is Samacsys:NJESD-30 代码:R-XDIP-T20
JESD-609代码:e0长度:25.4 mm
功能数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:UNSPECIFIED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified筛选级别:MIL-STD-883
座面最大高度:4.2418 mm标称供电电压:5 V
表面贴装:NO电信集成电路类型:MIL-STD-1553 DATA BUS TRANSCEIVER
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

ACT4468D 数据手册

 浏览型号ACT4468D的Datasheet PDF文件第1页浏览型号ACT4468D的Datasheet PDF文件第3页浏览型号ACT4468D的Datasheet PDF文件第4页浏览型号ACT4468D的Datasheet PDF文件第5页浏览型号ACT4468D的Datasheet PDF文件第6页 
a high impedance and is “removed”  
from the line. In addition, an  
overriding “INHIBIT" input provides  
for the removal of the transmitter  
output from the line. A logic “1”  
applied to the “INHIBIT” takes  
priority over the condition of the data  
inputs and disables the transmitter.  
(See Transmitter Logic Waveform,  
Figure 1.)  
Receiver:  
The Receiver section accepts  
bi-phase differential data at the input  
and produces two TTL signals at the  
output. The outputs are DATA and  
DATA, and represent positive and  
negative excursions of the input  
CIRCUIT TECHNOLOGY  
beyond  
threshold.(See  
Waveform. Figure 2.)  
a
pre-determined  
Receiver Logic  
The transceiver utilizes an active  
filter to suppress harmonics above  
1MHz. The Transmitter may be  
safely operated at 100% duty cycle  
for an indefinite period into a short  
circuited 1553 bus.  
The pre-set internal thresholds will  
detect data bus signals exceeding  
1.150 Volts P-P and reject signals  
less than 0.6 volts P-P when used  
with a 1:2.5 turns ratio transformer.  
(See Figure 5 for transformer data  
and typical connection.)  
Figure 1. Transmitter Logic Waveforms  
DATA IN  
DATA IN  
INHIBIT  
LINE TO LINE  
OUTPUT  
NOTES:  
1.DATA and DATA inputs must be complementary waveforms or 50% duty cycle average, with no delays between them.  
2.DATA and DATA must be in the same state during off time (both high or low).  
Figure 2. Receiver Logic Waveforms  
LINE TO LINE  
INPUT  
DATA OUT  
DATA OUT  
Note overlap  
NOTE: Waveforms shown are for normally low devices. For normally high receiver output  
level devices, the receiver outputs are swapped as shown by the dashed lines.  
2
Aeroflex Circuit Technology  
SCD4468D REV B 5/25/00 Plainview NY (516) 694-6700  

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