Datasheet > ACS8510_03

ACS8510_03

更新时间： 2022-12-20 01:55:00

品牌	Logo	应用领域
商升特 - SEMTECH		/
页数	文件大小	规格书
76页	789K
描述
Synchronous Equipment Timing Source for SONET or SDH Network Elements

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数据手册

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ACS8510_03 数据手册

ACS8510 Rev2.1 SETS

FINAL

ADVANCED COMMUNICATIONS

Table 3. Other Pins (continued)

SYMBOL

TYPE

TTL_D

NAME/DESCRIPTION

Synchronise 2 kHz: Connect to 2 kHz Multi-Frame Sync output of

partner ACS8510 in redundancy system

SYNC2K

TTL_D

Input reference 3: programmable, default 8 kHz

Input reference 4: programmable, default 8 kHz

Input reference 7: programmable, default 19.44 MHz

Input reference 8: programmable, default 19.44 MHz

Input reference 9: programmable, default 19.44 MHz

Input reference 10: programmable, default 19.44 MHz.

I10

Input reference 11: programmable,

default (master mode)1.544/2.048 MHz,

default (slave mode) 6.48 MHz

I11

TTL_D

I12

I13

I14

TTL_D

Input reference 12: programmable, default 1.544/2.048 MHz.

Input reference 13: programmable, default 1.544/2.048 MHz.

Input reference 14: programmable, default 1.544/2.048 MHz.

Microprocessor select: Configures the interface for a particular

microprocessor type.

58 - 60

63 - 69

UPSEL(2:0)

A(6:0)

TTL_D

TTL^U

Microprocessor Interface Address: Address bus for the

microprocessor interface registers. A(0) is SDI in Serial mode.

Chip Select (Active Low): This pin is asserted Low by the

microprocessor to enable the microprocessor interface.

CSB

Write (Active Low): This pin is asserted Low by the

microprocessor to initiate a write cycle. In Motorola mode, WRB = 1

for Read.

WRB

RDB

TTL^U

Read (Active Low): This pin is asserted Low by the

microprocessor to initiate a read cycle.

Address Latch Enable: This pin becomes the address latch

enable from the microprocessor. When this pin transitions from

Low to High, the address bus inputs are latched into the internal

registers. ALE = SCLK in Serial mode.

ALE

TTL_D

TTL^U

Power On Reset: Master reset. If PORB is forced Low, all internal

states are reset back to default values.

PORB

RDY

TTL

CMOS

Ready/Data acknowledge: This pin is asserted High to indicate

the device has completed a read or write operation.

Address/Data: Multiplexed data/address bus depending on the

microprocessor mode selection. AD(0) is SDO in Serial mode.

76 - 83

AD(7:0)

TTL_D

Revision 2.00/September 2003 Semtech Corp.

www.semtech.com

1...5 6 789 10 11...76

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ACS8510REV2.1	SEMTECH	Synchronous Equipment Timing Source for SONET or SDH Network Elements	获取价格
ACS8510REV2.1SETS	ETC	Synchronous Equipment Timing Source for SONET or SDH Network Elements	获取价格
ACS8510REV2.1T	SEMTECH	Support Circuit,	获取价格
ACS8510T	SEMTECH	暂无描述	获取价格
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