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AC82GL40/SLB95 PDF预览

AC82GL40/SLB95

更新时间: 2024-02-11 18:36:00
品牌 Logo 应用领域
英特尔 - INTEL /
页数 文件大小 规格书
460页 3140K
描述
Memory Controller, CMOS, PBGA1329

AC82GL40/SLB95 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.82JESD-30 代码:S-PBGA-B1329
端子数量:1329封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA1329,48X48,28
封装形状:SQUARE封装形式:GRID ARRAY, FINE PITCH
电源:1.05,1.5,1.8,3.3 V认证状态:Not Qualified
子类别:Memory Controllers表面贴装:YES
技术:CMOS端子形式:BALL
端子节距:0.7 mm端子位置:BOTTOM
Base Number Matches:1

AC82GL40/SLB95 数据手册

 浏览型号AC82GL40/SLB95的Datasheet PDF文件第7页浏览型号AC82GL40/SLB95的Datasheet PDF文件第8页浏览型号AC82GL40/SLB95的Datasheet PDF文件第9页浏览型号AC82GL40/SLB95的Datasheet PDF文件第11页浏览型号AC82GL40/SLB95的Datasheet PDF文件第12页浏览型号AC82GL40/SLB95的Datasheet PDF文件第13页 
Revision History  
Document Revision  
Description  
Date  
Number  
Number  
320122  
001  
• Initial Release  
Chapter 1  
July 2008  
— Added Section 1.3: GS45 Feature Support  
— Added Section 1.4: GL40 Feature Support  
Chapter 10  
— Added GS45 and GL40 power characteristic data to Table 24  
— Added GS45 and GL40 current data to Table 24  
— Added GS45 current data to Table 27  
320122  
002  
August 2008  
Section 13.3: Added clocking information for GS45 and GL40  
Section 16.4 and Section 16.5: Added Ballout and Signal Names  
for GS45  
Section 19.1.36: Added Configuration Register Description for  
GS45 and GL40  
• Chapter 1  
Section 1.3: Added GM47 Feature Support  
Section 1.3.3: Updated GS45 Graphics Core Render Clock  
Section 1.4.3: Updated GL40 Graphics Core Render Clock  
• Chapter 5  
Section 5.1:Added GS45 memory-down support on two  
channels  
• Chapter 10  
Section 10.1: Added GM47, updated GS45 and GL40 TDP  
numbers in Table 23  
Section 10.1: Added GM47, GS45 IVCC and updated GL40  
IVCC_AXG specification in Table 24  
Section 10.1: Added GM47 and GL40 IVCC_AXF specification  
in Table 27  
• Chapter 13  
Section 13.3: Added GM47 GMCH Clock Frequency Support  
Section 13.3: Added GL40 conversion stepping updates to  
320122  
003  
December 2008  
Clock Frequency Support  
• Chapter 16  
Section 16.3: Updated Intel 4 Series Express Chipset  
package drawing in Figure 25  
• Chapter 19  
Section 19.1.36: Added GM47 GFX Software and DDR2  
Capability and updated DDR3 and FSB Capability in CAPID  
Register  
• Chapter 20  
Section 20.4.4: Updated RST_EVNT definition in SLFRCS  
Register  
• Chapter 21  
Section 21.1.5: Added conversion A-1 stepping revision ID  
in RID Register  
• Chapter 23  
Section 23.1.1: Corrected Intel ME Identifier Register  
default value  
10  
Datasheet  

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