Datasheet > ABVFM-FREQ-R-L-T

ABVFM-FREQ-R-L-T

更新时间： 2024-12-02 04:03:31

品牌	Logo	应用领域
ABRACON		/
页数	文件大小	规格书
2页	1541K
描述
LVDS Output Clock Oscillator, 60MHz Min, 320MHz Max, CERAMIC, SMD, 6 PIN

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数据手册

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ABVFM-FREQ-R-L-T 数据手册

CERAMIC SMD CRRYYSSTTAALL CCLLOOCCKK OOSSCILLATOR

WWIITTHH VOLTAGE CONTROL

ABVFM SERIES

FEATURES:

: PRELIMINARY

5.0 x 7.0 x 1.8mm

APPLICATIONS:

• xDSL, Cable Modems

• Customer Premise Equipment (CPE)

• ATM, SONET, SDH, STB

• Based on a proprietary analog multiplier

• Tri-State Output

• Ultra low Phase Jitter

• 2.5V to 3.3V +/- 10% operation

• Ceramic SMD, low profile package

• LAN / WAN Data Communications Equip.

• 155.52MHz, 311.04MHz, 622.08MHz applications

STANDARD SPECIFICATIONS:

PARAMETERS

Frequency Range

60 MHz to 320 MHz

Operating Temperature

Storage Temperature

Overall Frequency Stability

Supply Voltage (Vdd)

Jitter (12KHz - 20MHz)

0°C to + 70°C (see options)

- 55°C to + 125°C

100 ppm maꢀx (see options)

2x5V - 3x3 Vdc 10ꢁ

RMS phase jitter < 0x6pS

period jitter < 20pS peak to peak

Low Phase Noise

-130 dBc/Hz @ 1kHz Offset from 212x5MHz

-140 dBc/Hz @ 10kHz Offset from 212x5MHz

-145 dBc/Hz @ 100kHz Offset from 212x5MHz

Aging (PPM/year)

Pullability

TBD Per Crystal

+/- 50ppm

PECL

Supply Current (I_DD)[Fout = 212x50MHz]

Output Clock Duty Cycle @ V_DD-1x3V

Output High Voltage

58mA min, 65mA typical, 75mA maꢀx

45ꢁ min, 50ꢁ typical, 55ꢁ maꢀx

V_OH= VDD-2V (VDD-1x025V min)

V_OL= VDD-2V (VDD-1x620V maꢀ)

0x7ns maꢀ, 0x4ns typical

Output Low Voltage

Clock Rise time (t_r) @ 20/80ꢁ

Clock Fall time (t_f) @ 80/20ꢁ

CMOS

0x7ns maꢀ, 0x4ns typical

Output Clock Rise/ Fall Time [10ꢁ~90ꢁ VDD with 10pF load] 1x6ns maꢀ, 1x2ns typical

Output Clock Duty Cycle [Measured @ 50ꢁ VDD]

LVDS

Supply Current (I_DD) [Fout = 212x50MHz]

Output Clock Duty Cycle @ 1x25V

45ꢁ min, 50ꢁ typical, 55ꢁ maꢀ

60mA maꢀ, 55mA typicalx

45ꢁ min, 50ꢁ typical, 55ꢁ maꢀ

247mV min, 355mV typical, 454mV maꢀ

-50mV min, 50mV maꢀ

Output Differential Voltage (V_OD

)

VDD Magnitude Change (∆V_OD

)

Output High Voltage

Output Low Voltage

Offset Voltage [R_L= 100

Offset Magnitude Voltage[RL = 100

Power-off Leakage (I_OXD) [Vout=VDD or GND, VDD=0V]

Differential Clock Rise Time (t_r) [R_L=100 , CL=10pF]

Differential Clock Fall Time (t_f) [R_L=100 , CL=10pF]

V_OH= 1x6V maꢀ, 1x4V typical

V_OL= 0x9V min, 1x1V typical

Ω]

V_OS= 1x125V min, 1x1V typical, 1x375V maꢀ

∆V_OS= 0mV min, 3mV typical, 25mV maꢀ

10µA maꢀ, 1µA typical

0x2ns min, 0x5ns typical, 0x7ns maꢀ

Ω]

Ω

ABBRRAACCOONN IIS

ISO 9001 / QS 9000

CERTTIIFFIED

30332 Esperanza, Rancho Santa Margarita, California 92688

tel 949-546-8000 | fax 949-546-8001 | www.abracon.com

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