Datasheet > AAT1235IRN-T1

AAT1235IRN-T1

更新时间： 2024-02-23 09:06:25

品牌	Logo	应用领域
ANALOGICTECH		驱动器
页数	文件大小	规格书
21页	958K
描述
High Efficiency White LED Drivers for Backlight and Keypad

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AAT1235IRN-T1 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.83
接口集成电路类型：	LED DISPLAY DRIVER	Base Number Matches：	1

AAT1235IRN-T1 数据手册

AAT1235

High Efficiency White LED Drivers

for Backlight and Keypad

Output capacitor size can be estimated at a switch-

ing frequency (F_S) of 500kHz (worst case):

To maintain stable operation at full load, the output

capacitor should be selected to maintain ΔV_OUT

between 100mV and 200mV.

The boost converter input current flows during both

ON and OFF switching intervals. The input ripple

current is less than the output ripple and, as a

result, less input capacitance is required.

I_OUT· D_MAX

F_S· ΔV_OUT

C_OUT

Manufacturer

Part Number

Value (µF) Voltage Rating Temp Co Case Size

Murata

GRM188R60J225KE19

GRM21BR71A225KA01

GRM219R61E225KA12

GRM21BR71E225KA73L

GRM21BR61E475KA12

2.2

4.7

6.3

X5R

X7R

X5R

X7R

X5R

0603

0805

Table 10: Recommended Ceramic Capacitors.

2. Minimize the distance between L1 to D1 and

switching pin SW; minimize the size of the PCB

area connected to the SW pin.

3. Maintain a ground plane and connect to the IC

GND pin(s) as well as the GND connections of

C1 and C2.

4. Consider additional PCB metal on D1’s cath-

ode to maximize heatsinking capability. This

may be necessary when using a diode with a

high V_Fand/or thermal resistance.

5. Do not connect the exposed paddle (bottom of

the die) to either AGND or GND because it is

connected internally to SW. Connect the

exposed paddle to the SW pin or leave floating.

PCB Layout Guidelines

Boost converter performance can be adversely

affected by poor layout. Possible impact includes

high input and output voltage ripple, poor EMI per-

formance, and reduced operating efficiency. Every

attempt should be made to optimize the layout in

order to minimize parasitic PCB effects (stray resist-

ance, capacitance, and inductance) and EMI cou-

pling from the high frequency SW node. A suggest-

ed PCB layout for the AAT1235 boost converter is

shown in Figures 4 and 5. The following PCB layout

guidelines should be considered:

1. Minimize the distance from Capacitor C1 and

C2’s negative terminals to the GND pins. This

is especially true with output capacitor C2,

which conducts high ripple current from the

output diode back to the GND pins.

1235.2007.02.1.1

1...15 16 171819 20 21

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与AAT1235IRN-T1相关器件

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