Datasheet > AAT1232_07

AAT1232_07

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
ANALOGICTECH		转换器升压转换器
页数	文件大小	规格书
18页	366K
描述
24V 100mA Step-Up Converter

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AAT1232_07 数据手册

AAT1232

24V 100mA Step-Up Converter

T_HI

T_OFF

T_LO

T_LAT

EN/SET

n-1

n ≤ 16

n-1

Data Reg

Figure 3: S Cwire Timing Diagram to Program the Output Voltage.

1. Minimize the distance from capacitor C1 and

C2 negative terminal to the PGND pins. This is

especially true with output capacitor C2, which

conducts high ripple current from the output

diode back to the PGND pins.

2. Place the feedback resistors close to the output

terminals. Route the output pin directly to resis-

tor R1 to maintain good output regulation. R3

should be routed close to the output GND pin.

3. Minimize the distance between L1 to D1 and

switching pin SW; minimize the size of the PCB

area connected to the SW pin.

4. Maintain a ground plane and connect to the IC

RTN pin(s) as well as the GND terminals of C1

and C2.

5. Consider additional PCB area on D1 cathode

to maximize heatsinking capability. This may

be necessary when using a diode with a high

thermal resistance.

6. When using the TDFN34-16 package, connect

paddle to SW pin or leave floating. Do not con-

nect to RTN/GND conductors.

7. To avoid problems at startup, add a 10kΩ resis-

tor between the VIN, VP and EN/SET pins (R4).

This is critical in applications requiring immuni-

ty from input noise during “hot plug” events, e.g.

when plugged into an active USB port.

S Cwire Output Voltage Programming

The AAT1232 is programmed through the S Cwire

interface according to Table 2. The rising clock

edges received through the EN/SET pin determine

the feedback reference and output voltage set-

point. Upon power up with the SEL pin low and

prior to S Cwire programming, the default feed-

back reference voltage is set to 0.6V.

PCB Layout Guidelines

Boost converter performance can be adversely

affected by poor layout. Possible impact includes

high input and output voltage ripple, poor EMI per-

formance, and reduced operating efficiency. Every

attempt should be made to optimize the layout in

order to minimize parasitic PCB effects (stray

resistance, capacitance, inductance) and EMI cou-

pling from the high frequency SW node.

A suggested PCB layout for the AAT1232 boost

converter is shown in Figures 4 and 5. The follow-

ing PCB layout guidelines should be considered:

1232.2007.06.1.5

1...11 12 131415 16 17 18

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