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A82DL1624UG-70I PDF预览

A82DL1624UG-70I

更新时间: 2024-02-16 04:22:38
品牌 Logo 应用领域
联笙电子 - AMICC 闪存静态存储器
页数 文件大小 规格书
57页 896K
描述
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x4T(U) 16 Megabit (2Mx8 Bit/1Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) S

A82DL1624UG-70I 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.69
Base Number Matches:1

A82DL1624UG-70I 数据手册

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A82DL16x4T(U) Series  
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM,  
A82DL16x4T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only,  
Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) Static RAM  
Preliminary  
DISTINCTIVE CHARACTERISTICS  
MCP Features  
- Suspends erase operations to allow programming in  
same bank  
Single power supply operation 2.7 to 3.6 volt  
High Performance  
- Access time as fast as 70ns  
Package 69-Ball TFBGA (8x11x1.4 mm)  
Industrial operating temperature range: -40°C to 85°C  
for –U; -25°C to 85°C for –I  
Polling and Toggle Bit  
Data  
- Provides a software method of detecting the status of  
program or erase cycles  
Unlock Bypass Program command  
- Reduces overall programming time when issuing  
multiple program command sequences  
Flash Features  
HARDWARE FEATURES  
Any combination of sectors can be erased  
ARCHITECTURAL ADVANTAGES  
Simultaneous Read/Write operations  
- Data can be continuously read from one bank while  
executing erase/program functions in other bank  
- Zero latency between read and write operations  
Multiple bank architectures  
- Three devices available with different bank sizes (refer to  
Table 2)  
Package  
Ready/  
output (RY/  
)
BY  
Busy  
- Hardware method for detecting program or erase cycle  
completion  
Hardware reset pin (  
)
RESET  
- Hardware method of resetting the internal state machine  
to reading array data  
/ACC input pin  
WP  
- 69-Ball TFBGA (8x11x1.4 mm)  
Top or bottom boot block  
- Write protect (  
outermost boot sectors, regardless of sector protect  
status  
) function allows protection of two  
WP  
Manufactured on 0.18 µm process technology  
- Compatible with AM42DL16x4D devices  
Compatible with JEDEC standards  
- Pinout and software compatible with single-power-supply  
flash standard  
- Acceleration (ACC) function accelerates program timing  
Sector protection  
- Hardware method of locking a sector, either in-system or  
using programming equipment, to prevent any program  
or erase operation within that sector  
PERFORMANCE CHARACTERISTICS  
High performance  
- Temporary Sector Unprotect allows changing data in  
protected sectors in-system  
- Access time as fast as 70ns  
- Program time: 7µs/word typical utilizing Accelerate  
function  
LP SRAM Features  
Ultra low power consumption (typical values)  
- 2mA active read current at 1MHz  
- 10mA active read current at 5MHz  
- 200nA in standby or automatic sleep mode  
Minimum 1 million write cycles guaranteed per sector  
20 Year data retention at 125°C  
- Reliable operation for the life of the system  
Power supply range: 2.7V to 3.6V  
Access times: 70 ns (max.)  
Current:  
Very low power version: Operating: 35mA(max.)  
Standby: 10uA (max.)  
Full static operation, no clock or refreshing required  
All inputs and outputs are directly TTL-compatible  
Common I/O using three-state output  
Output enable and two chips enable inputs for easy  
application  
SOFTWARE FEATURES  
Supports Common Flash Memory Interface (CFI)  
Erase Suspend/Erase Resume  
Data retention voltage: 2.0V (min.)  
PRELIMINARY (July, 2005, Version 0.0)  
1
AMIC Technology, Corp.  

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