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A8285

更新时间： 2024-02-07 09:33:27
品牌 Logo 应用领域
急速微 - ALLEGRO 稳压器
页数 文件大小 规格书
17页 526K
描述
LNB Supply and Control Voltage Regulator

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中文翻译

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A8285 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：BATWING, LEAD FREE, PLASTIC, SOIC-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.81模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：10.21 mm湿度敏感等级：3
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-20 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：10/16 V认证状态：Not Qualified
座面最大高度：2.64 mm子类别：Power Management Circuits
最大供电电流 (Isup)：7 mA最大供电电压 (Vsup)：16 V
最小供电电压 (Vsup)：10 V标称供电电压 (Vsup)：12 V
表面贴装：YES温度等级：OTHER
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.49 mm
Base Number Matches：1

A8285 数据手册

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A8285/A8287  
LNB Supply and Control Voltage Regulator  
Note: For the case of the A8287, the area of copper required  
on each layer is approximately 1.2 in2.  
Example.  
Given:  
Layout Considerations  
VIN = 12 V  
VOUT = 18 V  
Recommended placement of critical components and track-  
ing for the A8287 is shown in the PCB Layout digagram on  
the following page. It is recommended that the ground plane  
be separated into two areas, referred to as switcher and con-  
trol, on each layer using a ground plane. With respect to the  
input connections, VIN and 0V, the two ground plane areas  
are isolated as shown by the dotted line and the ground plane  
areas are connected together at pins 6, 7, 18, and 19. This  
configuration minimizes the effects of the noise produced by  
the switcher on the noise-sensitive sections of the circuit.  
ILOAD = 500 mA  
Two-layer PCB.  
Maximum ambient temperature = 70 ºC,  
Maximum allowed junction temperature= 110 ºC  
Assume:  
VD= 0.4 V and select ∆VREG= 0.7 V  
D = 1 – (12 / (18 + 0.4 + 0.7) = 0.37  
IPK = 18 0.5 / (0.89 12) = 843 mA  
Power-related tracking from INPUT to L1, LNB (pin 17) to  
L2 then OUTPUT, LX (pin 20) to D1 and L1, VBOOST (pin  
23) to C4 and D1 should be as short and wide as possible.  
Power components such as the boost diode D1, inductor  
L1, and input/output capacitors C1, C9, and C4, should be  
located as close as possible to the IC. The DiSEqC inductor  
L2 should be located as far away from the boost inductor L1  
to prevent potential magnetic crosstalk.  
×
×
×
RDSBOOST = 0.5 + (110– 25) 2.7 mΩ= 730 mΩ  
Worst case losses can now be estimated:  
Pd_Rds = 0.8432 0.73 0.37 = 192 mW  
× ×  
Pd_sw = 70 mW  
Pd_control = 15 mA  
VIN = 180 mW  
×
The filter capacitor (VREG), charge pump capacitor (VCP),  
ac coupling tone detect capacitor (TDI), tone pull-down  
resistor (TOUT), and LNB output capacitor/protection diode  
(LNB) should be located directly next to the appropriate pin.  
Pd_lin = 0.7 0.5 = 350 mW  
×
and therefore  
PTOT = 0.192 + 0.07 + 0.18 + 0.35 = 0.792 W  
Where a PCB with two or more layers is used, it is recom-  
mended that four thermal vias be deployed as shown in the  
PCB Layout diagram. Note that adding additional vias does  
not enhance the thermal characteristics.  
The thermal resistance required is:  
(110 – 70) / 0.792 = 50.5ºC/W  
RØJA vs. Area Charts  
A8285, 16-Pin SOIC  
A8287, 24-Pin SOIC  
100  
90  
80  
70  
60  
50  
80  
70  
60  
50  
40  
One side Copper  
Two side Copper  
One side Copper  
Two side Copper  
40  
0
0
1
2
3
4
1
2
3
4
Area(in.2)  
Area(in.2)  
12  
www.allegromicro.com  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
1...9101112131415...17

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