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A80960HA33SL2GY PDF预览

A80960HA33SL2GY

更新时间: 2024-02-13 21:17:37
品牌 Logo 应用领域
英特尔 - INTEL 微控制器和处理器外围集成电路微处理器时钟
页数 文件大小 规格书
102页 815K
描述
80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

A80960HA33SL2GY 技术参数

生命周期:Obsolete零件包装代码:PGA
包装说明:PGA, PGA168,17X17针数:168
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.74
地址总线宽度:32位大小:32
边界扫描:YES最大时钟频率:33 MHz
外部数据总线宽度:32格式:FIXED POINT
集成缓存:YESJESD-30 代码:S-CPGA-P168
长度:44.7 mm低功率模式:YES
端子数量:168最高工作温度:85 °C
最低工作温度:封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:PGA封装等效代码:PGA168,17X17
封装形状:SQUARE封装形式:GRID ARRAY
电源:3.3,3.3/5 V认证状态:Not Qualified
座面最大高度:4.57 mm速度:33 MHz
子类别:Microprocessors最大供电电压:3.45 V
最小供电电压:3.15 V标称供电电压:3.3 V
表面贴装:NO技术:CMOS
温度等级:OTHER端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
宽度:44.7 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

A80960HA33SL2GY 数据手册

 浏览型号A80960HA33SL2GY的Datasheet PDF文件第1页浏览型号A80960HA33SL2GY的Datasheet PDF文件第2页浏览型号A80960HA33SL2GY的Datasheet PDF文件第3页浏览型号A80960HA33SL2GY的Datasheet PDF文件第5页浏览型号A80960HA33SL2GY的Datasheet PDF文件第6页浏览型号A80960HA33SL2GY的Datasheet PDF文件第7页 
80960HA/HD/HT  
Figures  
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80960Hx Block Diagram .......................................................................................1  
80960Hx 168-Pin PGA Pinout — View from Top (Pins Facing Down) ...............12  
80960Hx 168-Pin PGA Pinout — View from Bottom (Pins Facing Up)...............13  
80960Hx 208-Pin PQ4 Pinout .............................................................................18  
Measuring 80960Hx PGA Case Temperature ....................................................23  
80960Hx Device Identification Register ..............................................................26  
VCC5 Current-Limiting Resistor..........................................................................30  
AC Test Load ......................................................................................................37  
CLKIN Waveform ................................................................................................38  
Output Delay Waveform......................................................................................38  
Output Delay Waveform......................................................................................38  
Output Float Waveform .......................................................................................39  
Input Setup and Hold Waveform .........................................................................39  
NMI, XINT7:0 Input Setup and Hold Waveform ..................................................39  
Hold Acknowledge Timings.................................................................................40  
Bus Backoff (BOFF) Timings ..............................................................................40  
TCK Waveform....................................................................................................41  
Input Setup and Hold Waveforms for TBSIS1 and TBSIH1 ....................................41  
Output Delay and Output Float for TBSOV1 and TBSOF1......................................42  
Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 ....................42  
Input Setup and Hold Waveform for TBSIS2 and TBSIH2 ......................................42  
Rise and Fall Time Derating at 85°C and Minimum VCC ....................................43  
ICC Active (Power Supply) vs. Frequency ...........................................................43  
ICC Active (Thermal) vs. Frequency ....................................................................44  
Output Delay or Hold vs. Load Capacitance .......................................................44  
Output Delay vs. Temperature ............................................................................45  
Output Hold Times vs. Temperature ...................................................................45  
Output Delay vs. VCC ..........................................................................................45  
Cold Reset Waveform .........................................................................................46  
Warm Reset Waveform.......................................................................................47  
Entering ONCE Mode .........................................................................................48  
Non-Burst, Non-Pipelined Requests without Wait States ...................................49  
Non-Burst, Non-Pipelined Read Request with Wait States.................................50  
Non-Burst, Non-Pipelined Write Request with Wait States.................................51  
Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus.................52  
Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus......................53  
Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus .................54  
Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus ......................55  
Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus......................56  
Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus........................57  
Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus.................58  
Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus......................59  
Burst, Pipelined Read Request without Wait States, 32-Bit Bus.........................60  
Burst, Pipelined Read Request with Wait States, 32-Bit Bus..............................61  
Burst, Pipelined Read Request with Wait States, 8-Bit Bus................................62  
Burst, Pipelined Read Request with Wait States, 16-Bit Bus..............................63  
Using External READY........................................................................................64  
Terminating a Burst with BTERM........................................................................65  
BREQ and BSTALL Operation............................................................................66  
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Advance Information Datasheet  

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