Datasheet > A6986F

A6986F

更新时间： 2022-02-26 10:37:26

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
72页	6721K
描述
38 V 1.5 A synchronous step-down switching regulator

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A6986F 数据手册

A6986F

Pin settings

2.1

Pin connection

Figure 2. Pin connection (top view)

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2.2

Pin description

Table 1. Pin description

Description

No.

The RST open collector output is driven low when the output voltage is out of regulation. The RST

is released after an adjustable time DELAY once the output voltage is over the active delay

threshold.

RST

Connect a ceramic capacitor (≥ 470 nF) to filter internal voltage reference. This pin supplies the

embedded analog circuitry.

VCC

An open collector stage can disable the device clamping this pin to GND (INH mode). An internal

current generator (2 A typ.) charges the external capacitor to implement the soft-start.

SS/INH

SYNCH/

ISKP

The pin features Master / Slave synchronization in LNM (see Section 5.5.1 on page 25) and skip

current level selection in LCM (see Section 5.5.2 on page 25).

A pull up resistor (E24 series only) to VCC or pull down to GND selects the switching frequency.

Pinstrapping is active only before the soft-start phase to minimize the IC consumption.

FSW

MLF

A pull up resistor (E24 series only) to VCC or pull down to GND selects the low noise mode/low

consumption mode and the active RST threshold. Pinstrapping is active only before the soft-start

phase to minimize the IC consumption.

COMP Output of the error amplifier. The designed compensation network is connected at this pin.

An external capacitor connected at this pin sets the time DELAY to assert the rising edge of the

DELAY RST o.c. after the output voltage is over the reset threshold. If this pin is left floating, RST is like

a Power Good.

VOUT

Output voltage sensing

SGND Signal GND

PGND Power GND

DocID027739 Rev 1

5/72

1 2 3 456 7 8...72

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