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A6801SLWTR-T

更新时间： 2024-02-28 22:59:12

品牌	Logo	应用领域
急速微 - ALLEGRO		驱动器
页数	文件大小	规格书
12页	435K
描述
Latch Based Peripheral Driver, 1 Driver, BICMOS, PDSO24, LEAD FREE, MS-013AD, SOIC-24

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技术参数
数据手册

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A6801SLWTR-T 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
ECCN代码：	EAR99	风险等级：	5.59
应用：	GENERAL PURPOSE	高度：	5.59 mm
绝缘电压：	1500 V	长度：	12.7 mm
安装特点：	SURFACE MOUNT	功能数量：	2
最高工作温度：	70 °C	最低工作温度：
包装方法：	TAPE & REEL	物理尺寸：	L12.7XB7.49XH5.59 (mm)
初级电感：	5.5 µH	最大脉冲上升时间：	0.35 ns
表面贴装：	YES	变压器类型：	DATACOM TRANSFORMER
匝数比 (Np:Ns)：	1CT:1CT	宽度：	7.49 mm
Base Number Matches：	1

A6801SLWTR-T 数据手册

A6800/A6801

DABiC-5 Latched Sink Drivers

Timing Requirements and Speciﬁcations

(Logic Levels are V_DDand Ground)

CLEAR

STROBE

OUTPUT

ENABLE

OUT

Key

Description

Time (ns)

Minimum data active time before Strobe enabled (Data Set-Up Time)

Minimum data active time after Strobe disabled (Data Hold Time)

Minimum Strobe pulse width

Maximum time between Strobe activation and transition from output on to output off*

Minimum time between Strobe activation and transition from output off to output on*

500

Maximum time between Output Enable activation and transition from output on to output off*

Minimum time between Output Enable activation and transition from output off to output on*

Minimum Clear pulse width

Minimum data pulse width

100

*Conditions for output transition testing are: V_DD= 50 V, V_CC= 5 V, R1 = 500 Ω, C1 ≤ 30 pF.

NOTE: Information present at an input is transferred

to its latch when the STROBE is high. A high CLEAR

input will set all latches to the output off condition

regardless of the data or STROBE input levels. A high

OUTPUT ENABLE will set all outputs to the off con-

tdition, regardless of any other input conditions. When

the OUTPUT ENABLE is low, the outputs depend on

the state of their respective latches.

www.allegromicro.com

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

1 2 345 6 7...12

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