Datasheet > 存储 > SRAM> A63L8336E-3.5

A63L8336E-3.5

更新时间： 2024-01-22 05:04:11

品牌	Logo	应用领域
联笙电子 - AMICC		计数器静态存储器
页数	文件大小	规格书
17页	257K
描述
256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output

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数据手册

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A63L8336E-3.5 数据手册

A63L8336

Timing Waveforms (continued)

CLK

ADSP

tKL

ADSS

tADSH

ADSC extends burst

ADSS

tADSH

ADSH

ADSS

ADSC

tAH

ADDRESS

BYTE WRITE signals are ignored

for first cycle when ADSP initiates burst

BWE,BW1-BW4

(NOTE *5)

tWH

CES

tCEH

(NOTE *2)

ADVS

ADVH

ADV

(NOTE *4)

ADV suspends burst

(NOTE *3)

tDH

D(A3+2)

High-Z

D(A1)

D(A2)

D(A2+1)

D(A2+2)

D(A2+3)

D(A3)

D(A3+1)

DIN

OEHZ

(NOTE *1)

DOUT

BURST READ

Single WRITE

Extended BURST WRITE

Write Timing

Notes: *1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately

following A2.

*2. Timing for CE2 and CE2 is identical to that for CE . As shown in the above diagram, when CE is LOW, CE2

is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.

*3. OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents

input/output data contention for the period prior to the time Byte Write enable inputs are sampled.

*4. ADV must be HIGH to permit a Write to the loaded address.

*5. Byte Write enables are decided by means of a Write truth table.

PRELIMINARY

(July, 2005, Version 0.0)

AMIC Technology, Corp.

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