Datasheet > A63L7336E-3.5F

A63L7336E-3.5F

更新时间： 2022-12-11 20:57:54

品牌	Logo	应用领域
联笙电子 - AMICC		计数器静态存储器
页数	文件大小	规格书
17页	257K
描述
128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output

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数据手册

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A63L7336E-3.5F 数据手册

A63L7336

Timing Waveforms

tKC

CLK

tKL

ADSS

ADSH

ADSP

ADSC

ADSS

tADSH

tAS

tAH

Burst continued with

ADDRESS

tWH

new base address

GW,BWE

BW1-BW4

Delselected

cycle

tCES

tCEH

(NOTE *2)

(NOTE *4)

ADVS

tADVH

ADV

ADV suspends

burst

OEHZ

tKQHZ

(NOTE *3)

OEQ

tKQ

OELZ

KQX

KQLZ

High-Z

Q(A1)

Q(A2)

Q(A2+1)

Q(A2+2)

Q(A2+3)

Q(A2)

Q(A3)

DOUT

Q(A2+1)

Burst wraps around

to its initial state

(NOTE *1)

Single READ

BURST READ

Read Timing

Notes:

*1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the internal burst address immediately

following A2.

*2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is

LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.

*3. Timing shown assumes that the device was not enabled before entering this sequence. OE does not cause Q to

be driven until after the rising edge of the following clock.

PRELIMINARY (July, 2005, Version 0.0)

AMIC Technology, Corp.

1...9 10 111213 14 15...17

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