A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
OPERATING CHARACTERISTICS
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max
Unit
ELECTRICAL CHARACTERISTICS valid at TA = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
LOGIC SUPPLY Voltage Range
VDD
Operating
VDD = 0.0 → 5.0 V
3.0
2.4
2.15
64.2
34.1
4.25
–
–
5.0
–
–
5.5
2.85
2.55
86.8
45.9
5.75
+6.0
+6.0
+6.0
5.0
V
V
V
mA
mA
mA
%
%
%
μA
V
V
Undervoltage Lockout
VDD(UV)
V
DD = 5.0 → 0.0 V
VCE = 0.7 V, REXT = 225 Ω
VCE = 0.7 V, REXT = 470 Ω
VCE = 0.6 V, REXT = 3900 Ω
VCE(A) = VCE(B) = 0.7 V, REXT = 225 Ω
VCE(A) = VCE(B) = 0.7 V, REXT = 470 Ω
75.5
40.0
5.0
+1.0
+1.0
+1.0
1.0
–
–
–
–
–
Output Current (any single output)
IO
Output Current Matching (difference between any two
ΔIO
outputs at the same VCE
Output Leakage Current
Logic Input Voltage
)
V
CE(A) = VCE(B) = 0.6 V, REXT = 3900 Ω
–
–
ICEX
VIH
VIL
VIhys
VOL
VOH
VOH = 15 V
0.7VDD
GND
200
–
VDD
0.3VDD
400
0.4
Logic Input Voltage Hysteresis
SERIAL DATA OUT Voltage
All digital inputs
IOL = 500 μA
IOH = –500 μA
mV
V
V
VDD–0.4
–
OUTPUT ENABLE input, Pull Up
LATCH ENABLE input, Pull Down
REXT = open, VOE = 5 V
150
100
–
–
–
–
–
–
–
300
200
–
–
–
–
–
–
600
400
1.4
5.0
8.0
kΩ
kΩ
mA
mA
mA
mA
mA
mA
°C
°C
V
Input Resistance
RI
IDD(OFF) REXT = 470 Ω, VOE = 5 V
REXT = 225 Ω, VOE = 5 V
LOGIC SUPPLY Current
REXT = 3900 Ω, VOE = 0 V
3.0
IDD(ON)
REXT = 470 Ω, VOE = 0 V
EXT = 225 Ω, VOE = 0 V
Temperature increasing
18.0
32.0
–
–
–
R
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Open LED Detection Threshold
TJTSD
TJTSDhys
165
15
0.30
–
–
VCE(ODC) IO > 5 mA, VCE ≥ 0.6 V
SWITCHING CHARACTERISTICS valid at TA = 25°C, VDD = VIH = 3.0 to 5.5 V, VCE = 0.7 V, VIL = 0 V, REXT = 470 Ω, IO = 40 mA, VLED = 3 V, RLED
=
58 Ω, CLED = 10 pF, unless otherwise noted
CLOCK Pulse Width
SERIAL DATA IN Setup Time
SERIAL DATA IN Hold Time
LATCH ENABLE Setup Time
LATCH ENABLE Hold Time
OUTPUT ENABLE Set Up Time
OUTPUT ENABLE Hold Time
OUTPUT ENABLE Pulse Width
CLOCK to SERIAL DATA OUT Propagation Delay Time
OUTPUT ENABLE to OUT0 Propagation Delay Time
Staggering Delay (between consecutive outputs)
Total Delay Time (15 × tD)
CLOCK Pulse Width
SERIAL DATA IN Setup Time
SERIAL DATA IN Hold Time
LATCH ENABLE Setup Time
LATCH ENABLE Hold Time
OUTPUT ENABLE Set Up Time
OUTPUT ENABLE Hold Time
OUTPUT ENABLE Pulse Width*
CLOCK to SERIAL DATA OUT Propagation Delay Time
OUTPUT ENABLE to OUT0 Propagation Delay Time
Staggering Delay (between consecutive outputs)
Total Delay Time (15 × tD)
thigh, tlow
tSU(D)
tH(D)
20
10
10
20
20
40
20
600
30
–
–
–
–
–
–
–
–
–
–
75
20
300
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
40
–
–
–
–
–
–
–
–
–
–
–
40
–
150
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
tSU(LE)
tH(LE)
tSU(OE)
tH(OE)
tW(OE)
tP(DO)
tP(OE)
tD
tDtotal
thigh, tlow
tSU(D)
tH(D)
tSU(LE)
tH(LE)
tSU(OE)
tH(OE)
tW(OE)
tP(DO)
tP(OE)
tD
Normal Mode
10
–
20
20
20
40
20
40
20
2.0
30
–
Test Mode, VDD = 4.5 to 5.5 V
–
–
75
20
300
75
75
10
–
–
tDtotal
tf
tr
Output Fall Time
Output Rise Time
90% to 10% voltage
10% to 90% voltage
–
*See LED Open Circuit Detection (Test) mode timing diagram.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com