Datasheet > A54SX32A-3FGG256

A54SX32A-3FGG256

更新时间： 2025-07-20 03:36:03

品牌	Logo	应用领域
ACTEL		栅
页数	文件大小	规格书
108页	793K
描述
Field Programmable Gate Array, 357MHz, 2880-Cell, CMOS, PBGA256

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A54SX32A-3FGG256 数据手册

SX-A Family FPGAs

different combinatorial functions to be implemented in a

single module. An example of the flexibility enabled by

the inversion capability is the ability to integrate a 3-input

exclusive-OR function into a single C-cell. This facilitates

construction of 9-bit parity-tree functions with 1.9 ns

propagation delays.

Logic Module Design

The SX-A family architecture is described as a “sea-of-

modules” architecture because the entire floor of the

device is covered with a grid of logic modules with

virtually no chip area lost to interconnect elements or

routing. The Actel SX-A family provides two types of

logic modules: the register cell (R-cell) and the

combinatorial cell (C-cell).

Module Organization

The R-cell contains a flip-flop featuring asynchronous clear,

asynchronous preset, and clock enable, using the S0 and S1

lines control signals (Figure 1-2). The R-cell registers feature

programmable clock polarity selectable on a register-by-

allowing mapping of synthesized functions into the SX-A

FPGA. The clock source for the R-cell can be chosen from

either the hardwired clock, the routed clocks, or internal

logic.

All C-cell and R-cell logic modules are arranged into

horizontal banks called Clusters. There are two types of

Clusters: Type 1 contains two C-cells and one R-cell, while

Type 2 contains one C-cell and two R-cells.

Clusters are grouped together into SuperClusters

(Figure 1-4 on page 1-3). SuperCluster 1 is a two-wide

grouping of Type 1 Clusters. SuperCluster 2 is a two-wide

group containing one Type 1 Cluster and one Type 2

Cluster. SX-A devices feature more SuperCluster 1

modules than SuperCluster 2 modules because designers

typically require significantly more combinatorial logic

than flip-flops.

The C-cell implements a range of combinatorial functions

of up to five inputs (Figure 1-3). Inclusion of the DB input

and its associated inverter function allows up to 4,000

Routed

Data Input

PRE

DirectConnect

Input

HCLK

CLKA,

CLR

CLKB,

Internal Logic

CKS

CKP

Figure 1-2 • R-Cell

A0 B0

Figure 1-3 • C-Cell

1-2

v5.3

1...3 4 567 8 9...108

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与A54SX32A-3FGG256相关器件

型号	品牌	获取价格	描述	数据表
A54SX32A-3FGG256A	ACTEL	获取价格	Field Programmable Gate Array, 2880 CLBs, 48000 Gates, CMOS, PBGA256, 1 MM, FBGA-256
A54SX32A-3FGG256I	ACTEL	获取价格	Field Programmable Gate Array, 357MHz, 2880-Cell, CMOS, PBGA256
A54SX32A-3FGG484	ACTEL	获取价格	Field Programmable Gate Array, 357MHz, 2880-Cell, CMOS, PBGA484
A54SX32A-3FGG484I	ACTEL	获取价格	Field Programmable Gate Array, 2880 CLBs, 48000 Gates, 357MHz, 2880-Cell, CMOS, PBGA484, 1
A54SX32A-3PQ208	ETC	获取价格	SX-A Family FPGAs
A54SX32A-3PQ208A	ETC	获取价格	SX-A Family FPGAs
A54SX32A-3PQ208AX79	MICROSEMI	获取价格	Field Programmable Gate Array, 2880-Cell, CMOS, PQFP208,
A54SX32A-3PQ208B	ETC	获取价格	SX-A Family FPGAs
A54SX32A-3PQ208I	ACTEL	获取价格	Field Programmable Gate Array, 2880 CLBs, 48000 Gates, 357MHz, 2880-Cell, CMOS, PQFP208, P
A54SX32A-3PQ208M	ETC	获取价格	SX-A Family FPGAs

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