Datasheet > A54SX32A-3TQ208

A54SX32A-3TQ208

更新时间： 2025-07-18 23:04:11

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
108页	720K
描述
SX-A Family FPGAs

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中文翻译

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数据手册

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A54SX32A-3TQ208 数据手册

v5.1

™

SX-A Family FPGAs

•

Configurable I/O Support for 3.3 V / 5 V PCI, 5 V

TTL, 3.3 V LVTTL, 2.5 V LVCMOS2

2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with

5 V Input Tolerance and 5 V Drive Strength

Devices Support Multiple Temperature Grades

Configurable Weak-Resistor Pull-Up or Pull-Down

for I/O at Power-Up

Individual Output Slew Rate Control

Up to 100% Resource Utilization and 100% Pin

Locking

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Leading-Edge Performance

•

250 MHz System Performance

350 MHz Internal Performance

•

Specifications

•

12,000 to 108,000 Available System Gates

Up to 360 User-Programmable I/O Pins

Up to 2,012 Dedicated Flip-Flops

•

0.22 µ / 0.25 µ CMOS Process Technology

Features

•

Boundary-Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

Actel Secure Programming Technology with

FuseLock™ Prevents Reverse Engineering and

Design Theft

•

Hot-Swap Compliant I/Os

Power-Up/Down Friendly (No Sequencing Required

for Supply Voltages)

•

66 MHz PCI Compliant

Nonvolatile, Single-Chip Solution

Table 1 • SX-A Product Profile

Device

A54SX08A

A54SX16A

A54SX32A

A54SX72A

Capacity

Typical Gates

System Gates

8,000

12,000

16,000

24,000

32,000

48,000

72,000

108,000

Logic Modules

768

512

256

1,452

924

528

2,880

1,800

1,080

1,980

6,036

4,024

2,012

4,024

Combinatorial Cells

Dedicated Flip-Flops

Maximum Flip-Flops

512*

990

Maximum User I/Os

Global Clocks

130

180

249

360

Quadrant Clocks

Boundary Scan Testing

3.3 V / 5 V PCI

Yes

Input Set-Up (External)

Speed Grades

0 ns

–F, Std, –1, –2

C, I, A, M

–F, Std, –1, –2, –3

C, I, A, M

–F, Std, –1, –2, –3

C, I, A, M

–F, Std, –1, –2, –3

C, I, A, M

Temperature Grades

Package (by pin count)

PQFP

TQFP

PBGA

FBGA

CQFP

208

100, 144, 176

329

144, 256, 484

208, 256

208

100, 144

–

144

–

144, 256

–

256, 484

208, 256

Note: *A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers

February 2005

See the Actel website for the latest version of the datasheet.

12 3 4 5 6 7...108

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与A54SX32A-3TQ208相关器件

型号	品牌	获取价格	描述	数据表
A54SX32A-3TQ208A	ETC	获取价格	SX-A Family FPGAs
A54SX32A-3TQ208B	ETC	获取价格	SX-A Family FPGAs
A54SX32A-3TQ208I	ETC	获取价格	SX-A Family FPGAs
A54SX32A-3TQ208M	ETC	获取价格	SX-A Family FPGAs
A54SX32A-3TQG100	ACTEL	获取价格	Field Programmable Gate Array, 357MHz, 2880-Cell, CMOS, PQFP100
A54SX32A-3TQG100A	ACTEL	获取价格	Field Programmable Gate Array, 2880 CLBs, 48000 Gates, CMOS, PQFP100, 1.40 MM, TQFP-100
A54SX32A-3TQG100I	ACTEL	获取价格	Field Programmable Gate Array, 357MHz, 2880-Cell, CMOS, PQFP100
A54SX32A-3TQG144	ACTEL	获取价格	Field Programmable Gate Array, 357MHz, 2880-Cell, CMOS, PQFP144
A54SX32A-3TQG144A	ACTEL	获取价格	Field Programmable Gate Array, 2880 CLBs, 48000 Gates, CMOS, PQFP144, 1.40 MM, TQFP-144
A54SX32A-3TQG144I	ACTEL	获取价格	Field Programmable Gate Array, 357MHz, 2880-Cell, CMOS, PQFP144

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