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A43L4616AV-7AF PDF预览

A43L4616AV-7AF

更新时间: 2024-02-09 00:44:57
品牌 Logo 应用领域
联笙电子 - AMICC 动态存储器
页数 文件大小 规格书
43页 492K
描述
DRAM

A43L4616AV-7AF 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.84

A43L4616AV-7AF 数据手册

 浏览型号A43L4616AV-7AF的Datasheet PDF文件第6页浏览型号A43L4616AV-7AF的Datasheet PDF文件第7页浏览型号A43L4616AV-7AF的Datasheet PDF文件第8页浏览型号A43L4616AV-7AF的Datasheet PDF文件第10页浏览型号A43L4616AV-7AF的Datasheet PDF文件第11页浏览型号A43L4616AV-7AF的Datasheet PDF文件第12页 
A43L4616A  
Operating AC Parameter  
(AC operating conditions unless otherwise noted)  
Version  
Symbol  
Parameter  
CAS  
Unit  
Note  
Latency  
-6  
12  
18  
-7  
14  
20  
-75  
15  
20  
tRRD(min)  
tRCD(min)  
Row active to row active delay  
ns  
ns  
1
1
RAS to  
delay  
CAS  
tRP(min)  
tRAS(min)  
tRAS(max)  
tRC(min)  
Row precharge time  
Row active time  
18  
42  
20  
45  
20  
45  
ns  
ns  
μs  
ns  
1
1
100  
60  
100  
63  
100  
65  
Row cycle time  
1
tCDL(min)  
tRDL(min)  
tDAL(min)  
tBDL(min)  
tCCD(min)  
tMRD(min)  
tREF(max)  
tARFC(min)  
Last data in new col. Address delay  
Last data in row precharge  
Last data in to Active delay  
Last data in to burst stop  
1
2
1
2
1
2
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
ms  
2
2
2,3  
5
5
5
1
1
1
2
Col. Address to col. Address delay  
Mode register set cycle time  
Refresh interval time  
1
1
1
2
2
2
64  
60  
64  
70  
64  
75  
Auto refresh cycle time  
ns  
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and  
then rounding off to the next higher integer.  
2. Minimum delay is required to complete write.  
PRELIMINARY (May, 2010, Version 0.4)  
8
AMIC Technology, Corp.  

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