Datasheet > A43L4616AV-7AF

A43L4616AV-7AF

更新时间： 2024-01-07 04:26:56

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
43页	492K
描述
DRAM

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技术参数
数据手册

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A43L4616AV-7AF 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84

A43L4616AV-7AF 数据手册

A43L4616A

Simplified Truth Table

Command

CKEn-1 CKEn

DQM BS0 A10 A9~A0,

Notes

CS RAS

CAS

BS1 /AP A11,A12

Mode Register Set

Auto Refresh

1,2

OP CODE

Refresh

Entry

Self

Refresh

Exit

Bank Active & Row Addr.

Row Addr.

Read &

Column Addr.

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

Column

Addr.

4,5

Write &

Column

Addr.

Column Addr.

4,5

Burst Stop

Precharge

Bank Selection

Both Banks

Entry

Clock Suspend or

Active Power Down

Exit

Entry

Precharge Power Down Mode

Exit

DQM

No Operation Command

(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)

Note : 1. OP Code: Operand Code

A0~A12, BS0, BS1: Program keys. (@MRS)

2. MRS can be issued only when all banks are at precharge state.

A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions as same as CBR refresh of DRAM.

The automatical precharge without Row precharge command is meant by “Auto”.

Auto/Self refresh can be issued only when all banks are at precharge state.

4. BS0, BS1 : Bank select address.

If both BS1 and BS0 are “Low” at read, write, row active and precharge, bank A is selected.

If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.

If both BS1 is “High” and BS0 is “Low” at read, write, row active and precharge, bank C is selected.

If both BS1 and BS0 are “High” at read, write, row active and precharge, bank D is selected.

If A10/AP is “High” at row precharge, BS1 and BS0 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command cannot be issued.

Another bank read/write command can be issued at every burst length.

6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)

but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)

PRELIMINARY (May, 2010, Version 0.4)

AMIC Technology, Corp.

1...7 8 91011 12 13...43

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