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A43L3616AG-6F PDF预览

A43L3616AG-6F

更新时间： 2024-02-14 13:57:07
品牌 Logo 应用领域
联笙电子 - AMICC 动态存储器内存集成电路
页数 文件大小 规格书
41页 629K
描述
DRAM

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A43L3616AG-6F 技术参数

是否Rohs认证： 符合生命周期：Contact Manufacturer
包装说明：VFBGA,Reach Compliance Code：unknown
风险等级：5.84访问模式：FOUR BANK PAGE BURST
最长访问时间：5.4 ns其他特性：AUTO/SELF REFRESH
JESD-30 代码：S-PBGA-B54长度：8 mm
内存密度：134217728 bit内存集成电路类型：SYNCHRONOUS DRAM
内存宽度：16功能数量：1
端口数量：1端子数量：54
字数：8388608 words字数代码：8000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8MX16
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：SQUARE封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1 mm
自我刷新：YES最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8 mm

A43L3616AG-6F 数据手册

 浏览型号A43L3616AG-6F的Datasheet PDF文件第7页浏览型号A43L3616AG-6F的Datasheet PDF文件第8页浏览型号A43L3616AG-6F的Datasheet PDF文件第9页浏览型号A43L3616AG-6F的Datasheet PDF文件第11页浏览型号A43L3616AG-6F的Datasheet PDF文件第12页浏览型号A43L3616AG-6F的Datasheet PDF文件第13页 
A43L3616A Series  
Simplified Truth Table  
Command  
CKEn-1 CKEn CS RAS  
DQM BA0 A10 A9~A0,  
BA1 /AP A11  
Notes  
CAS  
L
WE  
L
Register  
Mode Register Set  
Auto Refresh  
1,2  
H
H
X
L
L
X
X
OP CODE  
3
3
3
Refresh  
H
L
L
L
L
L
H
H
X
Entry  
Self  
H
H
Refresh  
Exit  
L
H
X
X
X
X
H
L
X
L
X
H
X
H
3
4
Bank Active & Row Addr.  
H
V
V
Row Addr.  
Read &  
Column Addr.  
Auto Precharge Disable  
Auto Precharge Enable  
Auto Precharge Disable  
Auto Precharge Enable  
L
Column  
Addr.  
4
H
X
L
H
L
H
X
H
L
4,5  
4
Write &  
Column  
Addr.  
H
H
X
X
L
L
H
H
L
L
L
X
X
V
Column Addr.  
H
4,5  
Reserved  
Precharge  
H
X
Bank Selection  
Both Banks  
V
X
L
H
X
L
L
H
L
X
X
H
L
H
X
L
H
X
X
H
X
V
X
X
H
X
H
X
X
H
X
V
X
H
X
X
H
X
V
X
Entry  
H
L
L
H
L
X
X
X
Clock Suspend or  
Active Power Down  
X
X
Exit  
Entry  
H
H
L
Precharge Power Down Mode  
Exit  
L
H
H
H
X
X
V
X
H
DQM  
X
X
6
L
H
X
H
X
No Operation Command  
H
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)  
Note : 1. OP Code: Operand Code  
A0~A11, BA0, BA1: Program keys. (@MRS)  
2. MRS can be issued only at both banks precharge state.  
A new command can be issued after 2 clock cycle of MRS.  
3. Auto refresh functions as same as CBR refresh of DRAM.  
The automatical precharge without Row precharge command is meant by “Auto”.  
Auto/Self refresh can be issued only at both precharge state.  
4. BA0, BA1 : Bank select address.  
If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.  
If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.  
If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.  
If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected.  
If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.  
5. During burst read or write with auto precharge, new read write command cannot be issued.  
Another bank read write command can be issued at every burst length.  
6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)  
but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)  
PRELIMINARY (November, 2011, Version 0.8)  
9
AMIC Technology, Corp.  
1...78910111213...41

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