Datasheet > A43L1632AG-5UF

A43L1632AG-5UF

更新时间： 2022-12-01 19:23:56

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
43页	740K
描述
DRAM

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数据手册

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A43L1632AG-5UF 数据手册

A43L1632A

Operating AC Parameter

(AC operating conditions unless otherwise noted)

Version

Symbol

Parameter

Unit

Note

-5

-5.5

-6

-7

tRRD(min)

tRCD(min)

Row active to row active delay

CLK

RAS to

delay

CAS

tRP(min)

tRAS(min)

tRAS(max)

tRC(min)

Row precharge time

Row active time

CLK

μs

100

Row cycle time

CLK

tRDL(min)

tCDL(min)

tBDL(min)

tCCD(min)

Last data in to row precharge

Last data in to new col. Address delay

Last data in to burst stop

CLK

Col. Address to col. address delay

CAS Latency = 3

CAS Latency = 2

Number of valid output

data

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

PRELIMINARY (March, 2007, Version 0.0)

AMIC Technology, Corp.

1...7 8 91011 12 13...43

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