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A42L8316S-30 PDF预览

A42L8316S-30

更新时间: 2022-11-25 16:57:13
品牌 Logo 应用领域
联笙电子 - AMICC /
页数 文件大小 规格书
25页 274K
描述
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE

A42L8316S-30 数据手册

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A42L8316 Series  
Preliminary  
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE  
Features  
nOrganization: 262,144 words X 16 bits  
nPart Identification  
nIndustrial operating temperature range: -40°C to 85°C  
for -U  
nFast Page Mode with Extended Data Out  
- A42L8316 (512 Ref.)  
n Single 3.3V power supply/built-in VBB generator  
nLow power consumption  
- Operating: 110mA (-30 max)  
- Standby: 2.5mA (TTL), 1.5mA (CMOS)  
1.0mA (Self-refresh current)  
nHigh speed  
nSeparate  
(
,
) for byte selection  
UCAS LCAS  
CAS  
n512 Refresh Cycle in 8ms  
nRead-modify-write, RAS -only, CAS -before- RAS ,  
Hidden refresh capability  
nTTL-compatible, three-state I/O  
nJEDEC standard packages  
- 30/35/40 ns RAS access time  
- 16/17/18 ns column address access time  
- 400mil, 40-pin SOJ  
- 400mil, 40/44 TSOP type II package  
- 9/10/11 ns CAS access time  
- 14/16/18 ns EDO Page Mode Cycle Time  
This allow random access of up to 512 words within a row  
at a 71/62/55 MHz EDO cycle, making the A42L8316  
ideally suited for graphics, digital signal processing and  
high performance computing systems.  
General Description  
The A42L8316 is a new generation randomly accessed  
memory for graphics, organized in a 262,144-word by 16-  
bit configuration. This product can execute Byte Write  
and Byte Read operation via two  
pins.  
CAS  
The A42L8316 offers an accelerated Fast Page Mode  
Pin Descriptions  
Pin Configuration  
Symbol  
Description  
Address Inputs  
nSOJ  
n TSOP  
A0 – A8  
I/O0 - I/O15 Data Input/Output  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
VSS  
I/O15  
I/O14  
I/O13  
I/O12  
VSS  
I/O11  
I/O10  
I/O9  
VCC  
1
VSS  
VCC  
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
I/O4  
I/O5  
I/O6  
I/O7  
1
I/O0  
I/O1  
2
2
I/O15  
I/O14  
Row Address Strobe  
RAS  
3
3
I/O2  
I/O3  
VCC  
I/O4  
I/O5  
I/O6  
I/O7  
NC  
I/O13  
I/O12  
VSS  
I/O11  
I/O10  
I/O9  
I/O8  
NC  
4
4
Column Address Strobe for Lower Byte  
LCAS  
UCAS  
WE  
5
5
6
6
(I/O0 – I/O7)  
7
7
Column Address Strobe for Upper Byte  
(I/O8 – I/O15)  
8
8
9
9
10  
11  
12  
13  
14  
15  
10  
I/O8  
Write Enable  
32  
31  
30  
29  
28  
27  
26  
25  
NC  
LCAS  
UCAS  
OE  
NC  
NC  
NC  
WE  
RAS  
NC  
A0  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
LCAS  
UCAS  
WE  
RAS  
NC  
A0  
A1  
A2  
Output Enable  
OE  
A8  
OE  
VCC  
VSS  
NC  
3.3V Power Supply  
Ground  
A7  
A6  
16  
17  
18  
19  
20  
A8  
A7  
A6  
A5  
A1  
A2  
A5  
A4  
VSS  
No Connection  
A3  
VCC  
22  
21  
24  
23  
A4  
A3  
VSS  
VCC  
cycle with a feature called Extended Data Out (EDO).  
PRELIMINARY  
(August, 2002, Version 0.1)  
1
AMIC Technology, Inc.  

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